Add a wishlist FIXME

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scottmcm 2023-10-06 07:05:09 +00:00 committed by GitHub
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@ -52,6 +52,8 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
#[no_mangle]
// CHECK-LABEL: @wider_reduce_into_iter
pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
// FIXME: It would be nice if this was exactly the same as the above tests,
// but at the time of writing this comment, that didn't happen on LLVM main.
// CHECK: call i16 @llvm.vector.reduce.add
x.to_array().into_iter().map(u16::from).sum()
}