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add a csky-unknown-linux-gnuabiv2 target

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This commit is contained in:
Dirreke 2023-07-13 22:19:59 +08:00 committed by dirreke
parent 3071e0aef6
commit d16409fe22
30 changed files with 313 additions and 4 deletions
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1
compiler/rustc_codegen_gcc/example/alloc_system.rs
View File

@ -12,6 +12,7 @@
target_arch = "mips",
target_arch = "mips32r6",
target_arch = "powerpc",
target_arch = "csky"
target_arch = "powerpc64"))]
const MIN_ALIGN: usize = 8;
#[cfg(any(target_arch = "x86_64",

5
compiler/rustc_codegen_gcc/src/asm.rs
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@ -597,6 +597,8 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "d", // more specific than "r"
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Msp430(Msp430InlineAsmRegClass::reg) => "r",
@ -673,6 +675,8 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Msp430(_) => unimplemented!(),
@ -860,6 +864,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
InlineAsmRegClass::S390x(_) => None,
InlineAsmRegClass::Msp430(_) => None,
InlineAsmRegClass::M68k(_) => None,
InlineAsmRegClass::CSKY(_) => None,
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}

6
compiler/rustc_codegen_llvm/src/asm.rs
View File

@ -261,6 +261,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
InlineAsmArch::M68k => {
constraints.push("~{ccr}".to_string());
}
InlineAsmArch::CSKY => {} // https://github.com/llvm/llvm-project/blob/8b76aea8d8b1b71f6220bc2845abc749f18a19b7/clang/lib/Basic/Targets/CSKY.h getClobers()
}
}
if !options.contains(InlineAsmOptions::NOMEM) {
@ -693,6 +694,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
@ -792,6 +795,7 @@ fn modifier_to_llvm(
bug!("LLVM backend does not support SPIR-V")
}
InlineAsmRegClass::M68k(_) => None,
InlineAsmRegClass::CSKY(_) => None,
InlineAsmRegClass::Err => unreachable!(),
}
}
@ -868,6 +872,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => cx.type_i32(),
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::CSKY(CSKYInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}

1
compiler/rustc_llvm/build.rs
View File

@ -12,6 +12,7 @@ const OPTIONAL_COMPONENTS: &[&str] = &[
"avr",
"loongarch",
"m68k",
"csky",
"mips",
"powerpc",
"systemz",

7
compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp
View File

@ -105,6 +105,12 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
#define SUBTARGET_M68K
#endif
#ifdef LLVM_COMPONENT_CSKY
#define SUBTARGET_CSKY SUBTARGET(CSKY)
#else
#define SUBTARGET_CSKY
#endif
#ifdef LLVM_COMPONENT_MIPS
#define SUBTARGET_MIPS SUBTARGET(Mips)
#else
@ -159,6 +165,7 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
SUBTARGET_AARCH64 \
SUBTARGET_AVR \
SUBTARGET_M68K \
SUBTARGET_CSKY \
SUBTARGET_MIPS \
SUBTARGET_PPC \
SUBTARGET_SYSTEMZ \

8
compiler/rustc_llvm/src/lib.rs
View File

@ -102,6 +102,14 @@ pub fn initialize_available_targets() {
LLVMInitializeM68kAsmPrinter,
LLVMInitializeM68kAsmParser
);
init_target!(
llvm_component = "csky",
LLVMInitializeCSKYTargetInfo,
LLVMInitializeCSKYTarget,
LLVMInitializeCSKYTargetMC,
LLVMInitializeCSKYAsmPrinter,
LLVMInitializeCSKYAsmParser
);
init_target!(
llvm_component = "loongarch",
LLVMInitializeLoongArchTargetInfo,

31
compiler/rustc_target/src/abi/call/csky.rs Normal file
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@ -0,0 +1,31 @@
//see https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYCallingConv.td
use crate::abi::call::{ArgAbi, FnAbi};
fn classify_ret<Ty>(ret: &mut ArgAbi<'_, Ty>) {
if ret.layout.is_aggregate() || ret.layout.size.bits() > 64 {
ret.make_indirect();
} else {
ret.extend_integer_width_to(32);
}
}
fn classify_arg<Ty>(arg: &mut ArgAbi<'_, Ty>) {
if arg.layout.is_aggregate() || arg.layout.size.bits() > 64 {
arg.make_indirect();
} else {
arg.extend_integer_width_to(32);
}
}
pub fn compute_abi_info<Ty>(fn_abi: &mut FnAbi<'_, Ty>) {
if !fn_abi.ret.is_ignore() {
classify_ret(&mut fn_abi.ret);
}
for arg in fn_abi.args.iter_mut() {
if arg.is_ignore() {
continue;
}
classify_arg(arg);
}
}

2
compiler/rustc_target/src/abi/call/mod.rs
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@ -9,6 +9,7 @@ mod amdgpu;
mod arm;
mod avr;
mod bpf;
mod csky;
mod hexagon;
mod loongarch;
mod m68k;
@ -712,6 +713,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
"avr" => avr::compute_abi_info(self),
"loongarch64" => loongarch::compute_abi_info(cx, self),
"m68k" => m68k::compute_abi_info(self),
"csky" => csky::compute_abi_info(self),
"mips" | "mips32r6" => mips::compute_abi_info(cx, self),
"mips64" | "mips64r6" => mips64::compute_abi_info(cx, self),
"powerpc" => powerpc::compute_abi_info(self),

142
compiler/rustc_target/src/asm/csky.rs Normal file
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@ -0,0 +1,142 @@
use super::{InlineAsmArch, InlineAsmType};
use rustc_macros::HashStable_Generic;
use rustc_span::Symbol;
use std::fmt;
def_reg_class! {
CSKY CSKYInlineAsmRegClass {
reg,
freg,
}
}
impl CSKYInlineAsmRegClass {
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
&[]
}
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
None
}
pub fn suggest_modifier(
self,
_arch: InlineAsmArch,
_ty: InlineAsmType,
) -> Option<(char, &'static str)> {
None
}
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
None
}
pub fn supported_types(
self,
_arch: InlineAsmArch,
) -> &'static [(InlineAsmType, Option<Symbol>)] {
match self {
Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
Self::freg => types! { _: F32, F64; },
}
}
}
// The reserved registers are taken from <https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp#79>
def_regs! {
CSKY CSKYInlineAsmReg CSKYInlineAsmRegClass {
r0: reg = ["r0","a0"],
r1: reg = ["r1","a1"],
r2: reg = ["r2","a2"],
r3: reg = ["r3","a3"],
r4: reg = ["r4","l0"],
r5: reg = ["r5","l1"],
r6: reg = ["r6","l2"],
// r7: reg = ["r7","l3"],
// r8: reg = ["r8","l4"],
// r9: reg = ["r9","l5"],
// r10: reg = ["r10","l6"],
// r11: reg = ["r11","l7"],
// r12: reg = ["r12","t0"],
// r13: reg = ["r13","t1"],
// r14: reg = ["r14","sp"],
// r15: reg = ["r15","lr"],
// r16: reg = ["r16","l8"],
// r17: reg = ["r17","l9"],
// r18: reg = ["r18","t2"],
// r19: reg = ["r19","t3"],
// r20: reg = ["r20","t4"],
// r21: reg = ["r21","t5"],
// r22: reg = ["r22","t6"],
// r23: reg = ["r23","t7", "fp"],
// r24: reg = ["r24","t8", "sop"],
// r25: reg = ["r25","tp", "bsp"],
// r26: reg = ["r26"],
// r27: reg = ["r27"],
// r28: reg = ["r28","gb", "rgb", "rdb"],
// r29: reg = ["r29","tb", "rtb"],
// r30: reg = ["r30","svbr"],
// r31: reg = ["r31","tls"],
f0: freg = ["fr0","vr0"],
f1: freg = ["fr1","vr1"],
f2: freg = ["fr2","vr2"],
f3: freg = ["fr3","vr3"],
f4: freg = ["fr4","vr4"],
f5: freg = ["fr5","vr5"],
f6: freg = ["fr6","vr6"],
f7: freg = ["fr7","vr7"],
f8: freg = ["fr8","vr8"],
f9: freg = ["fr9","vr9"],
f10: freg = ["fr10","vr10"],
f11: freg = ["fr11","vr11"],
f12: freg = ["fr12","vr12"],
f13: freg = ["fr13","vr13"],
f14: freg = ["fr14","vr14"],
f15: freg = ["fr15","vr15"],
f16: freg = ["fr16","vr16"],
f17: freg = ["fr17","vr17"],
f18: freg = ["fr18","vr18"],
f19: freg = ["fr19","vr19"],
f20: freg = ["fr20","vr20"],
f21: freg = ["fr21","vr21"],
f22: freg = ["fr22","vr22"],
f23: freg = ["fr23","vr23"],
f24: freg = ["fr24","vr24"],
f25: freg = ["fr25","vr25"],
f26: freg = ["fr26","vr26"],
f27: freg = ["fr27","vr27"],
f28: freg = ["fr28","vr28"],
f29: freg = ["fr29","vr29"],
f30: freg = ["fr30","vr30"],
f31: freg = ["fr31","vr31"],
#error = ["r7", "l3"] =>
"the base pointer cannot be used as an operand for inline asm",
#error = ["r8","l4"] =>
"the frame pointer cannot be used as an operand for inline asm",
#error = ["r14","sp"] =>
"the stack pointer cannot be used as an operand for inline asm",
#error = ["r15","lr"] =>
"the link register cannot be used as an operand for inline asm",
#error = ["r31","tls"] =>
"reserver for tls",
#error = ["r28", "gb", "rgb", "rdb"] =>
"the global pointer cannot be used as an operand for inline asm",
#error = ["r9","l5", "r10","l6", "r11","l7", "r12","t0", "r13","t1"] =>
"reserved (no E2)",
#error = ["r16","l8", "r17","l9", "r18","t2", "r19","t3", "r20","t4", "r21","t5", "r22","t6", "r23","t7", "fp", "r24","t8", "sop", "r25","tp", "bsp"] =>
"reserved (no HighRegisters)",
#error = ["r26","r27","r29","tb", "rtb", "r30","svbr"] =>
"reserved by the ABI",
}
}
impl CSKYInlineAsmReg {
pub fn emit(
self,
out: &mut dyn fmt::Write,
_arch: InlineAsmArch,
_modifier: Option<char>,
) -> fmt::Result {
out.write_str(self.name())
}
}

24
compiler/rustc_target/src/asm/mod.rs
View File

@ -167,6 +167,7 @@ mod aarch64;
mod arm;
mod avr;
mod bpf;
mod csky;
mod hexagon;
mod loongarch;
mod m68k;
@ -184,6 +185,7 @@ pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
pub use avr::{AvrInlineAsmReg, AvrInlineAsmRegClass};
pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};
pub use csky::{CSKYInlineAsmReg, CSKYInlineAsmRegClass};
pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
pub use loongarch::{LoongArchInlineAsmReg, LoongArchInlineAsmRegClass};
pub use m68k::{M68kInlineAsmReg, M68kInlineAsmRegClass};
@ -220,6 +222,7 @@ pub enum InlineAsmArch {
Avr,
Msp430,
M68k,
CSKY,
}
impl FromStr for InlineAsmArch {
@ -248,6 +251,7 @@ impl FromStr for InlineAsmArch {
"avr" => Ok(Self::Avr),
"msp430" => Ok(Self::Msp430),
"m68k" => Ok(Self::M68k),
"csky" => Ok(Self::CSKY),
_ => Err(()),
}
}
@ -272,6 +276,7 @@ pub enum InlineAsmReg {
Avr(AvrInlineAsmReg),
Msp430(Msp430InlineAsmReg),
M68k(M68kInlineAsmReg),
CSKY(CSKYInlineAsmReg),
// Placeholder for invalid register constraints for the current target
Err,
}
@ -292,6 +297,7 @@ impl InlineAsmReg {
Self::Avr(r) => r.name(),
Self::Msp430(r) => r.name(),
Self::M68k(r) => r.name(),
Self::CSKY(r) => r.name(),
Self::Err => "<reg>",
}
}
@ -311,6 +317,7 @@ impl InlineAsmReg {
Self::Avr(r) => InlineAsmRegClass::Avr(r.reg_class()),
Self::Msp430(r) => InlineAsmRegClass::Msp430(r.reg_class()),
Self::M68k(r) => InlineAsmRegClass::M68k(r.reg_class()),
Self::CSKY(r) => InlineAsmRegClass::CSKY(r.reg_class()),
Self::Err => InlineAsmRegClass::Err,
}
}
@ -344,6 +351,7 @@ impl InlineAsmReg {
InlineAsmArch::Avr => Self::Avr(AvrInlineAsmReg::parse(name)?),
InlineAsmArch::Msp430 => Self::Msp430(Msp430InlineAsmReg::parse(name)?),
InlineAsmArch::M68k => Self::M68k(M68kInlineAsmReg::parse(name)?),
InlineAsmArch::CSKY => Self::CSKY(CSKYInlineAsmReg::parse(name)?),
})
}
@ -371,6 +379,7 @@ impl InlineAsmReg {
Self::Avr(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
Self::Msp430(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
Self::M68k(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
Self::CSKY(r) => r.validate(arch, reloc_model, target_features, target, is_clobber),
Self::Err => unreachable!(),
}
}
@ -397,6 +406,7 @@ impl InlineAsmReg {
Self::Avr(r) => r.emit(out, arch, modifier),
Self::Msp430(r) => r.emit(out, arch, modifier),
Self::M68k(r) => r.emit(out, arch, modifier),
Self::CSKY(r) => r.emit(out, arch, modifier),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
}
}
@ -416,6 +426,7 @@ impl InlineAsmReg {
Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))),
Self::Msp430(_) => cb(self),
Self::M68k(_) => cb(self),
Self::CSKY(_) => cb(self),
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
}
}
@ -440,6 +451,7 @@ pub enum InlineAsmRegClass {
Avr(AvrInlineAsmRegClass),
Msp430(Msp430InlineAsmRegClass),
M68k(M68kInlineAsmRegClass),
CSKY(CSKYInlineAsmRegClass),
// Placeholder for invalid register constraints for the current target
Err,
}
@ -463,6 +475,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.name(),
Self::Msp430(r) => r.name(),
Self::M68k(r) => r.name(),
Self::CSKY(r) => r.name(),
Self::Err => rustc_span::symbol::sym::reg,
}
}
@ -488,6 +501,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Avr),
Self::Msp430(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Msp430),
Self::M68k(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::M68k),
Self::CSKY(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::CSKY),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
}
@ -520,6 +534,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.suggest_modifier(arch, ty),
Self::Msp430(r) => r.suggest_modifier(arch, ty),
Self::M68k(r) => r.suggest_modifier(arch, ty),
Self::CSKY(r) => r.suggest_modifier(arch, ty),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
}
@ -548,6 +563,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.default_modifier(arch),
Self::Msp430(r) => r.default_modifier(arch),
Self::M68k(r) => r.default_modifier(arch),
Self::CSKY(r) => r.default_modifier(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
}
@ -575,6 +591,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.supported_types(arch),
Self::Msp430(r) => r.supported_types(arch),
Self::M68k(r) => r.supported_types(arch),
Self::CSKY(r) => r.supported_types(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
}
@ -607,6 +624,7 @@ impl InlineAsmRegClass {
InlineAsmArch::Avr => Self::Avr(AvrInlineAsmRegClass::parse(name)?),
InlineAsmArch::Msp430 => Self::Msp430(Msp430InlineAsmRegClass::parse(name)?),
InlineAsmArch::M68k => Self::M68k(M68kInlineAsmRegClass::parse(name)?),
InlineAsmArch::CSKY => Self::CSKY(CSKYInlineAsmRegClass::parse(name)?),
})
}
@ -630,6 +648,7 @@ impl InlineAsmRegClass {
Self::Avr(r) => r.valid_modifiers(arch),
Self::Msp430(r) => r.valid_modifiers(arch),
Self::M68k(r) => r.valid_modifiers(arch),
Self::CSKY(r) => r.valid_modifiers(arch),
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
}
}
@ -826,6 +845,11 @@ pub fn allocatable_registers(
m68k::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
map
}
InlineAsmArch::CSKY => {
let mut map = csky::regclass_map();
csky::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
map
}
}
}

22
compiler/rustc_target/src/spec/csky_unknown_linux_gnuabiv2.rs Normal file
View File

@ -0,0 +1,22 @@
use crate::spec::{Target, TargetOptions};
// This target is for glibc Linux on Csky
// hardfloat.
pub fn target() -> Target {
Target {
//https://github.com/llvm/llvm-project/blob/8b76aea8d8b1b71f6220bc2845abc749f18a19b7/clang/lib/Basic/Targets/CSKY.h
llvm_target: "csky-unknown-linux".into(),
pointer_width: 32,
data_layout: "e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32-v128:32:32-a:0:32-Fi32-n32".into(),
arch: "csky".into(),
options: TargetOptions {
abi: "abiv2".into(),
//+hard-float, +hard-float-abi, +fpuv2_sf, +fpuv2_df, +fpuv3_sf, +fpuv3_df, +vdspv2, +dspv2, +vdspv1, +3e3r1
features: "".into(),
max_atomic_width: Some(32),
// mcount: "\u{1}__gnu_mcount_nc".into(),
..super::linux_gnu_base::opts()
},
}
}

1
compiler/rustc_target/src/spec/mod.rs
View File

@ -1246,6 +1246,7 @@ supported_targets! {
("i586-unknown-linux-gnu", i586_unknown_linux_gnu),
("loongarch64-unknown-linux-gnu", loongarch64_unknown_linux_gnu),
("m68k-unknown-linux-gnu", m68k_unknown_linux_gnu),
("csky-unknown-linux-gnuabiv2", csky_unknown_linux_gnuabiv2),
("mips-unknown-linux-gnu", mips_unknown_linux_gnu),
("mips64-unknown-linux-gnuabi64", mips64_unknown_linux_gnuabi64),
("mips64el-unknown-linux-gnuabi64", mips64el_unknown_linux_gnuabi64),

2
config.example.toml
View File

@ -94,7 +94,7 @@ changelog-seen = 2
# the same format as above, but since these targets are experimental, they are
# not built by default and the experimental Rust compilation targets that depend
# on them will not work unless the user opts in to building them.
#experimental-targets = "AVR;M68k"
#experimental-targets = "AVR;M68k;CSKY"
# Cap the number of parallel linker invocations when compiling LLVM.
# This can be useful when building LLVM with debug info, which significantly

3
library/core/src/ffi/mod.rs
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@ -110,7 +110,8 @@ mod c_char_definition {
target_arch = "powerpc64",
target_arch = "s390x",
target_arch = "riscv64",
target_arch = "riscv32"
target_arch = "riscv32",
target_arch = "csky"
)
),
all(target_os = "android", any(target_arch = "aarch64", target_arch = "arm")),

1
library/std/src/env.rs
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@ -894,6 +894,7 @@ pub mod consts {
/// - aarch64
/// - loongarch64
/// - m68k
/// - csky
/// - mips
/// - mips64
/// - powerpc

1
library/std/src/os/l4re/raw.rs
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@ -27,6 +27,7 @@ pub use self::arch::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t};
#[cfg(any(
target_arch = "x86",
target_arch = "m68k",
target_arch = "csky",
target_arch = "powerpc",
target_arch = "sparc",
target_arch = "arm",

1
library/std/src/os/linux/raw.rs
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@ -27,6 +27,7 @@ pub use self::arch::{blkcnt_t, blksize_t, ino_t, nlink_t, off_t, stat, time_t};
#[cfg(any(
target_arch = "x86",
target_arch = "m68k",
target_arch = "csky",
target_arch = "powerpc",
target_arch = "sparc",
target_arch = "arm",

1
library/std/src/sys/common/alloc.rs
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@ -8,6 +8,7 @@ use crate::ptr;
target_arch = "x86",
target_arch = "arm",
target_arch = "m68k",
target_arch = "csky",
target_arch = "mips",
target_arch = "mips32r6",
target_arch = "powerpc",

3
library/std/src/sys/personality/gcc.rs
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@ -67,6 +67,9 @@ const UNWIND_DATA_REG: (i32, i32) = (0, 1); // D0, D1
))]
const UNWIND_DATA_REG: (i32, i32) = (4, 5); // A0, A1
#[cfg(target_arch = "csky")]
const UNWIND_DATA_REG: (i32, i32) = (0, 1); // R0, R1
#[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))]
const UNWIND_DATA_REG: (i32, i32) = (3, 4); // R3, R4 / X3, X4

3
library/unwind/src/libunwind.rs
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@ -54,6 +54,9 @@ pub const unwinder_private_data_size: usize = 2;
#[cfg(any(target_arch = "mips", target_arch = "mips32r6"))]
pub const unwinder_private_data_size: usize = 2;
#[cfg(target_arch = "csky")]
pub const unwinder_private_data_size: usize = 2;
#[cfg(any(target_arch = "mips64", target_arch = "mips64r6"))]
pub const unwinder_private_data_size: usize = 2;

1
src/bootstrap/bootstrap.py
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@ -332,6 +332,7 @@ def default_build_triple(verbose):
'i786': 'i686',
'loongarch64': 'loongarch64',
'm68k': 'm68k',
'csky': 'csky',
'powerpc': 'powerpc',
'powerpc64': 'powerpc64',
'powerpc64le': 'powerpc64le',

2
src/bootstrap/lib.rs
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@ -138,7 +138,7 @@ const EXTRA_CHECK_CFGS: &[(Option<Mode>, &'static str, Option<&[&'static str]>)]
(
Some(Mode::Std),
"target_arch",
Some(&["asmjs", "spirv", "nvptx", "xtensa", "mips32r6", "mips64r6"]),
Some(&["asmjs", "spirv", "nvptx", "xtensa", "mips32r6", "mips64r6", "csky"]),
),
/* Extra names used by dependencies */
// FIXME: Used by serde_json, but we should not be triggering on external dependencies.

2
src/bootstrap/llvm.rs
View File

@ -299,7 +299,7 @@ impl Step for Llvm {
let llvm_exp_targets = match builder.config.llvm_experimental_targets {
Some(ref s) => s,
None => "AVR;M68k",
None => "AVR;M68k;CSKY",
};
let assertions = if builder.config.llvm_assertions { "ON" } else { "OFF" };

1
src/doc/rustc/src/SUMMARY.md
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@ -32,6 +32,7 @@
- [\*-esp-espidf](platform-support/esp-idf.md)
- [\*-unknown-fuchsia](platform-support/fuchsia.md)
- [\*-kmc-solid_\*](platform-support/kmc-solid.md)
- [csky-unknown-linux-gnuabiv2](platform-support/csky-unknown-linux-gnuabiv2.md)
- [loongarch\*-unknown-linux-\*](platform-support/loongarch-linux.md)
- [loongarch\*-unknown-none\*](platform-support/loongarch-none.md)
- [m68k-unknown-linux-gnu](platform-support/m68k-unknown-linux-gnu.md)

1
src/doc/rustc/src/platform-support.md
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@ -259,6 +259,7 @@ target | std | host | notes
`avr-unknown-gnu-atmega328` | * | | AVR. Requires `-Z build-std=core`
`bpfeb-unknown-none` | * | | BPF (big endian)
`bpfel-unknown-none` | * | | BPF (little endian)
`csky-unknown-linux-gnuabiv2` | ? | | C-SKY iv2 Linux
`hexagon-unknown-linux-musl` | ? | |
`i386-apple-ios` | ✓ | | 32-bit x86 iOS
[`i586-pc-nto-qnx700`](platform-support/nto-qnx.md) | * | | 32-bit x86 QNX Neutrino 7.0 RTOS |

33
src/doc/rustc/src/platform-support/csky-unknown-linux-gnuabiv2.md Normal file
View File

@ -0,0 +1,33 @@
# `csky-unknown-linux-gnuabiv2`
**Tier: 3**
This target supports [C-SKY](https://github.com/c-sky) v2 CPUs with `glibc`.
https://c-sky.github.io/
## Target maintainers
* [@Dirreke](https://github.com/Dirreke)
## Requirements
## Building the target
add `csky-unknown-linux-gnuabiv2` to the `target` list in `config.toml` and `./x build`.
## Building Rust programs
Rust programs can be built for that target:
```text
cargo +stage2 --target csky-unknown-linux-gnuabiv2 your-code.rs
```
## Testing
Currently there is no support to run the rustc test suite for this target.
## Cross-compilation toolchains and C code
This target can be cross-compiled from `x86_64` on either Linux systems with [`csky-linux-gunabiv2-tools-x86_64-glibc-linux`](https://github.com/c-sky/toolchain-build).

9
src/doc/unstable-book/src/language-features/asm-experimental-arch.md
View File

@ -17,6 +17,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
- AVR
- MSP430
- M68k
- CSKY
- s390x
## Register classes
@ -46,6 +47,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
| M68k | `reg` | `d[0-7]`, `a[0-7]` | `r` |
| M68k | `reg_data` | `d[0-7]` | `d` |
| M68k | `reg_addr` | `a[0-3]` | `a` |
| CSKY | `reg` | `r[0-31]` | `r` |
| CSKY | `freg` | `f[0-31]` | `f` |
| s390x | `reg` | `r[0-10]`, `r[12-14]` | `r` |
| s390x | `freg` | `f[0-15]` | `f` |
@ -79,6 +82,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
| MSP430 | `reg` | None | `i8`, `i16` |
| M68k | `reg`, `reg_addr` | None | `i16`, `i32` |
| M68k | `reg_data` | None | `i8`, `i16`, `i32` |
| CSKY | `reg` | None | `i8`, `i16`, `i32`, `i64` |
| CSKY | `freg` | None | `f32`, `f64` |
| s390x | `reg` | None | `i8`, `i16`, `i32`, `i64` |
| s390x | `freg` | None | `f32`, `f64` |
@ -102,6 +107,10 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
| M68k | `a5` | `bp` |
| M68k | `a6` | `fp` |
| M68k | `a7` | `sp`, `usp`, `ssp`, `isp` |
| CSKY | `r14` | `sp` |
| CSKY | `r15` | `lr` |
| CSKY | `r28` | `gb`, `rgb`, `rdb` |
| CSKY | `r31` | `tls` |
> **Notes**:
> - TI does not mandate a frame pointer for MSP430, but toolchains are allowed

1
src/librustdoc/clean/cfg.rs
View File

@ -519,6 +519,7 @@ impl<'a> fmt::Display for Display<'a> {
"asmjs" => "JavaScript",
"loongarch64" => "LoongArch LA64",
"m68k" => "M68k",
"csky" => "CSKY",
"mips" => "MIPS",
"mips32r6" => "MIPS Release 6",
"mips64" => "MIPS-64",

1
src/tools/build-manifest/src/main.rs
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@ -100,6 +100,7 @@ static TARGETS: &[&str] = &[
"i686-unknown-uefi",
"loongarch64-unknown-linux-gnu",
"m68k-unknown-linux-gnu",
"csky-unknown-linux-gnuabiv2",
"mips-unknown-linux-gnu",
"mips-unknown-linux-musl",
"mips64-unknown-linux-gnuabi64",

1
src/tools/rust-analyzer/crates/ide-completion/src/completions/attribute/cfg.rs
View File

@ -46,6 +46,7 @@ const KNOWN_ARCH: [&str; 19] = [
"aarch64",
"arm",
"avr",
"csky",
"hexagon",
"mips",
"mips64",