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Add Hexagon support
This requires an updated LLVM with D31999 and D32000 to build libcore. A basic hello world builds and runs successfully on the hexagon simulator.
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@ -94,7 +94,7 @@ fn main() {
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let optional_components =
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["x86", "arm", "aarch64", "mips", "powerpc", "pnacl", "systemz", "jsbackend", "msp430",
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"sparc", "nvptx"];
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"sparc", "nvptx", "hexagon"];
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// FIXME: surely we don't need all these components, right? Stuff like mcjit
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// or interpreter the compiler itself never uses.
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@ -382,6 +382,12 @@ pub fn initialize_available_targets() {
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LLVMInitializeNVPTXTarget,
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LLVMInitializeNVPTXTargetMC,
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LLVMInitializeNVPTXAsmPrinter);
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init_target!(llvm_component = "hexagon",
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LLVMInitializeHexagonTargetInfo,
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LLVMInitializeHexagonTarget,
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LLVMInitializeHexagonTargetMC,
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LLVMInitializeHexagonAsmPrinter,
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LLVMInitializeHexagonAsmParser);
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}
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pub fn last_error() -> Option<String> {
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@ -29,6 +29,7 @@ use cabi_sparc;
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use cabi_sparc64;
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use cabi_nvptx;
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use cabi_nvptx64;
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use cabi_hexagon;
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use machine::llalign_of_min;
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use type_::Type;
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use type_of;
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@ -896,6 +897,7 @@ impl<'a, 'tcx> FnType<'tcx> {
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"sparc64" => cabi_sparc64::compute_abi_info(ccx, self),
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"nvptx" => cabi_nvptx::compute_abi_info(ccx, self),
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"nvptx64" => cabi_nvptx64::compute_abi_info(ccx, self),
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"hexagon" => cabi_hexagon::compute_abi_info(ccx, self),
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a => ccx.sess().fatal(&format!("unrecognized arch \"{}\" in target specification", a))
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}
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43
src/librustc_trans/cabi_hexagon.rs
Normal file
43
src/librustc_trans/cabi_hexagon.rs
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@ -0,0 +1,43 @@
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// Copyright 2012-2013 The Rust Project Developers. See the COPYRIGHT
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// file at the top-level directory of this distribution and at
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// http://rust-lang.org/COPYRIGHT.
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//
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// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
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// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
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// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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#![allow(non_upper_case_globals)]
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use abi::{FnType, ArgType, LayoutExt};
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use context::CrateContext;
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fn classify_ret_ty<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>, ret: &mut ArgType<'tcx>) {
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if ret.layout.is_aggregate() && ret.layout.size(ccx).bits() > 64 {
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ret.make_indirect(ccx);
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} else {
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ret.extend_integer_width_to(32);
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}
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}
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fn classify_arg_ty<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>, arg: &mut ArgType<'tcx>) {
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if arg.layout.is_aggregate() && arg.layout.size(ccx).bits() > 64 {
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arg.make_indirect(ccx);
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} else {
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arg.extend_integer_width_to(32);
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}
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}
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pub fn compute_abi_info<'a, 'tcx>(ccx: &CrateContext<'a, 'tcx>, fty: &mut FnType<'tcx>) {
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if !fty.ret.is_ignore() {
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classify_ret_ty(ccx, &mut fty.ret);
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}
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for arg in &mut fty.args {
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if arg.is_ignore() {
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continue;
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}
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classify_arg_ty(ccx, arg);
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}
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}
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@ -97,6 +97,7 @@ mod builder;
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mod cabi_aarch64;
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mod cabi_arm;
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mod cabi_asmjs;
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mod cabi_hexagon;
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mod cabi_mips;
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mod cabi_mips64;
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mod cabi_msp430;
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@ -147,6 +147,12 @@ extern "C" void LLVMRustAddPass(LLVMPassManagerRef PMR, LLVMPassRef RustPass) {
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#define SUBTARGET_SPARC
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#endif
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#ifdef LLVM_COMPONENT_HEXAGON
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#define SUBTARGET_HEXAGON SUBTARGET(Hexagon)
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#else
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#define SUBTARGET_HEXAGON
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#endif
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#define GEN_SUBTARGETS \
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SUBTARGET_X86 \
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SUBTARGET_ARM \
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@ -155,7 +161,8 @@ extern "C" void LLVMRustAddPass(LLVMPassManagerRef PMR, LLVMPassRef RustPass) {
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SUBTARGET_PPC \
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SUBTARGET_SYSTEMZ \
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SUBTARGET_MSP430 \
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SUBTARGET_SPARC
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SUBTARGET_SPARC \
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SUBTARGET_HEXAGON
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#define SUBTARGET(x) \
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namespace llvm { \
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