Make target-cpu=native detect individual features

compiler/rustc_codegen_llvm/src/back/write.rs

@@ -164,7 +164,8 @@ pub fn target_machine_factory(
 
     let code_model = to_llvm_code_model(sess.code_model());
 
-    let features = attributes::llvm_target_features(sess).collect::<Vec<_>>();
+    let mut features = llvm_util::handle_native_features(sess);
+    features.extend(attributes::llvm_target_features(sess).map(|s| s.to_owned()));
     let mut singlethread = sess.target.singlethread;
 
     // On the wasm target once the `atomics` feature is enabled that means that

compiler/rustc_codegen_llvm/src/lib.rs

@@ -12,6 +12,7 @@
 #![feature(in_band_lifetimes)]
 #![feature(nll)]
 #![feature(or_patterns)]
+#![feature(stdsimd)]
 #![recursion_limit = "256"]
 
 use back::write::{create_informational_target_machine, create_target_machine};

compiler/rustc_codegen_llvm/src/llvm_util.rs

@@ -10,6 +10,7 @@ use rustc_span::symbol::Symbol;
 use rustc_target::spec::{MergeFunctions, PanicStrategy};
 use std::ffi::CString;
 
+use std::detect;
 use std::slice;
 use std::str;
 use std::sync::atomic::{AtomicBool, Ordering};
@@ -221,6 +222,25 @@ pub fn target_cpu(sess: &Session) -> &str {
     handle_native(name)
 }
 
+pub fn handle_native_features(sess: &Session) -> Vec<String> {
+    const LLVM_NOT_RECOGNIZED: &[&str] = &["tsc"];
+
+    match sess.opts.cg.target_cpu {
+        Some(ref s) => {
+            if s != "native" {
+                return vec![];
+            }
+
+            detect::features()
+                .map(|(feature, support)| (to_llvm_feature(sess, feature), support))
+                .filter(|(feature, _)| !LLVM_NOT_RECOGNIZED.contains(feature))
+                .map(|(feature, support)| (if support { "+" } else { "-" }).to_owned() + feature)
+                .collect()
+        }
+        None => vec![],
+    }
+}
+
 pub fn tune_cpu(sess: &Session) -> Option<&str> {
     match sess.opts.debugging_opts.tune_cpu {
         Some(ref s) => Some(handle_native(&**s)),