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Remove from cranelift codegen LLVM intrinsics that are no longer needed
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@ -32,41 +32,6 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
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ret.write_cvalue(fx, CValue::by_val(res, fx.layout_of(fx.tcx.types.i64)));
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}
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// Used by `_mm_movemask_epi8` and `_mm256_movemask_epi8`
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"llvm.x86.sse2.pmovmskb.128"
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| "llvm.x86.avx2.pmovmskb"
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| "llvm.x86.sse.movmsk.ps"
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| "llvm.x86.sse2.movmsk.pd" => {
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intrinsic_args!(fx, args => (a); intrinsic);
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let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
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let lane_ty = fx.clif_type(lane_ty).unwrap();
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assert!(lane_count <= 32);
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let mut res = fx.bcx.ins().iconst(types::I32, 0);
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for lane in (0..lane_count).rev() {
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let a_lane = a.value_lane(fx, lane).load_scalar(fx);
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// cast float to int
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let a_lane = match lane_ty {
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types::F32 => codegen_bitcast(fx, types::I32, a_lane),
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types::F64 => codegen_bitcast(fx, types::I64, a_lane),
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_ => a_lane,
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};
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// extract sign bit of an int
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let a_lane_sign = fx.bcx.ins().ushr_imm(a_lane, i64::from(lane_ty.bits() - 1));
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// shift sign bit into result
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let a_lane_sign = clif_intcast(fx, a_lane_sign, types::I32, false);
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res = fx.bcx.ins().ishl_imm(res, 1);
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res = fx.bcx.ins().bor(res, a_lane_sign);
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}
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let res = CValue::by_val(res, fx.layout_of(fx.tcx.types.i32));
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ret.write_cvalue(fx, res);
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}
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"llvm.x86.sse.cmp.ps" | "llvm.x86.sse2.cmp.pd" => {
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let (x, y, kind) = match args {
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[x, y, kind] => (x, y, kind),
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