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Auto merge of #106975 - tmiasko:basic-blocks-cache, r=cjgillot
Refactor basic blocks control flow caches No functional changes.
This commit is contained in:
commit
a5fa99eed2
@ -1,38 +1,44 @@
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use crate::mir::graph_cyclic_cache::GraphIsCyclicCache;
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use crate::mir::predecessors::{PredecessorCache, Predecessors};
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use crate::mir::switch_sources::{SwitchSourceCache, SwitchSources};
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use crate::mir::traversal::PostorderCache;
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use crate::mir::{BasicBlock, BasicBlockData, Successors, START_BLOCK};
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use crate::mir::traversal::Postorder;
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use crate::mir::{BasicBlock, BasicBlockData, Successors, Terminator, TerminatorKind, START_BLOCK};
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use rustc_data_structures::fx::FxHashMap;
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use rustc_data_structures::graph;
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use rustc_data_structures::graph::dominators::{dominators, Dominators};
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use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
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use rustc_data_structures::sync::OnceCell;
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use rustc_index::vec::IndexVec;
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use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
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use smallvec::SmallVec;
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#[derive(Clone, TyEncodable, TyDecodable, Debug, HashStable, TypeFoldable, TypeVisitable)]
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pub struct BasicBlocks<'tcx> {
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basic_blocks: IndexVec<BasicBlock, BasicBlockData<'tcx>>,
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predecessor_cache: PredecessorCache,
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switch_source_cache: SwitchSourceCache,
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is_cyclic: GraphIsCyclicCache,
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postorder_cache: PostorderCache,
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cache: Cache,
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}
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// Typically 95%+ of basic blocks have 4 or fewer predecessors.
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pub type Predecessors = IndexVec<BasicBlock, SmallVec<[BasicBlock; 4]>>;
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pub type SwitchSources = FxHashMap<(BasicBlock, BasicBlock), SmallVec<[Option<u128>; 1]>>;
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#[derive(Clone, Default, Debug)]
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struct Cache {
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predecessors: OnceCell<Predecessors>,
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switch_sources: OnceCell<SwitchSources>,
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is_cyclic: OnceCell<bool>,
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postorder: OnceCell<Vec<BasicBlock>>,
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}
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impl<'tcx> BasicBlocks<'tcx> {
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#[inline]
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pub fn new(basic_blocks: IndexVec<BasicBlock, BasicBlockData<'tcx>>) -> Self {
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BasicBlocks {
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basic_blocks,
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predecessor_cache: PredecessorCache::new(),
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switch_source_cache: SwitchSourceCache::new(),
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is_cyclic: GraphIsCyclicCache::new(),
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postorder_cache: PostorderCache::new(),
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}
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BasicBlocks { basic_blocks, cache: Cache::default() }
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}
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/// Returns true if control-flow graph contains a cycle reachable from the `START_BLOCK`.
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#[inline]
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pub fn is_cfg_cyclic(&self) -> bool {
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self.is_cyclic.is_cyclic(self)
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*self.cache.is_cyclic.get_or_init(|| graph::is_cyclic(self))
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}
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#[inline]
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@ -43,20 +49,46 @@ impl<'tcx> BasicBlocks<'tcx> {
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/// Returns predecessors for each basic block.
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#[inline]
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pub fn predecessors(&self) -> &Predecessors {
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self.predecessor_cache.compute(&self.basic_blocks)
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self.cache.predecessors.get_or_init(|| {
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let mut preds = IndexVec::from_elem(SmallVec::new(), &self.basic_blocks);
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for (bb, data) in self.basic_blocks.iter_enumerated() {
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if let Some(term) = &data.terminator {
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for succ in term.successors() {
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preds[succ].push(bb);
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}
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}
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}
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preds
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})
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}
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/// Returns basic blocks in a postorder.
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#[inline]
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pub fn postorder(&self) -> &[BasicBlock] {
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self.postorder_cache.compute(&self.basic_blocks)
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self.cache.postorder.get_or_init(|| {
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Postorder::new(&self.basic_blocks, START_BLOCK).map(|(bb, _)| bb).collect()
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})
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}
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/// `switch_sources()[&(target, switch)]` returns a list of switch
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/// values that lead to a `target` block from a `switch` block.
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#[inline]
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pub fn switch_sources(&self) -> &SwitchSources {
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self.switch_source_cache.compute(&self.basic_blocks)
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self.cache.switch_sources.get_or_init(|| {
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let mut switch_sources: SwitchSources = FxHashMap::default();
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for (bb, data) in self.basic_blocks.iter_enumerated() {
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if let Some(Terminator {
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kind: TerminatorKind::SwitchInt { targets, .. }, ..
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}) = &data.terminator
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{
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for (value, target) in targets.iter() {
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switch_sources.entry((target, bb)).or_default().push(Some(value));
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}
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switch_sources.entry((targets.otherwise(), bb)).or_default().push(None);
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}
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}
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switch_sources
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})
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}
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/// Returns mutable reference to basic blocks. Invalidates CFG cache.
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@ -88,10 +120,7 @@ impl<'tcx> BasicBlocks<'tcx> {
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/// All other methods that allow you to mutate the basic blocks also call this method
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/// themselves, thereby avoiding any risk of accidentally cache invalidation.
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pub fn invalidate_cfg_cache(&mut self) {
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self.predecessor_cache.invalidate();
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self.switch_source_cache.invalidate();
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self.is_cyclic.invalidate();
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self.postorder_cache.invalidate();
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self.cache = Cache::default();
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}
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}
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@ -145,3 +174,24 @@ impl<'tcx> graph::WithPredecessors for BasicBlocks<'tcx> {
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self.predecessors()[node].iter().copied()
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}
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}
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TrivialTypeTraversalAndLiftImpls! {
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Cache,
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}
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impl<S: Encoder> Encodable<S> for Cache {
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#[inline]
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fn encode(&self, _s: &mut S) {}
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}
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impl<D: Decoder> Decodable<D> for Cache {
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#[inline]
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fn decode(_: &mut D) -> Self {
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Default::default()
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}
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}
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impl<CTX> HashStable<CTX> for Cache {
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#[inline]
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fn hash_stable(&self, _: &mut CTX, _: &mut StableHasher) {}
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}
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@ -1,63 +0,0 @@
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use rustc_data_structures::graph::{
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self, DirectedGraph, WithNumNodes, WithStartNode, WithSuccessors,
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};
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use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
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use rustc_data_structures::sync::OnceCell;
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use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
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/// Helper type to cache the result of `graph::is_cyclic`.
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#[derive(Clone, Debug)]
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pub(super) struct GraphIsCyclicCache {
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cache: OnceCell<bool>,
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}
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impl GraphIsCyclicCache {
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#[inline]
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pub(super) fn new() -> Self {
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GraphIsCyclicCache { cache: OnceCell::new() }
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}
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pub(super) fn is_cyclic<G>(&self, graph: &G) -> bool
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where
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G: ?Sized + DirectedGraph + WithStartNode + WithSuccessors + WithNumNodes,
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{
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*self.cache.get_or_init(|| graph::is_cyclic(graph))
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}
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/// Invalidates the cache.
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#[inline]
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pub(super) fn invalidate(&mut self) {
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// Invalidating the cache requires mutating the MIR, which in turn requires a unique
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// reference (`&mut`) to the `mir::Body`. Because of this, we can assume that all
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// callers of `invalidate` have a unique reference to the MIR and thus to the
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// cache. This means we never need to do synchronization when `invalidate` is called,
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// we can simply reinitialize the `OnceCell`.
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self.cache = OnceCell::new();
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}
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}
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impl<S: Encoder> Encodable<S> for GraphIsCyclicCache {
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#[inline]
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fn encode(&self, s: &mut S) {
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Encodable::encode(&(), s);
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}
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}
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impl<D: Decoder> Decodable<D> for GraphIsCyclicCache {
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#[inline]
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fn decode(d: &mut D) -> Self {
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let () = Decodable::decode(d);
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Self::new()
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}
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}
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impl<CTX> HashStable<CTX> for GraphIsCyclicCache {
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#[inline]
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fn hash_stable(&self, _: &mut CTX, _: &mut StableHasher) {
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// do nothing
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}
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}
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TrivialTypeTraversalAndLiftImpls! {
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GraphIsCyclicCache,
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}
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@ -47,18 +47,15 @@ mod basic_blocks;
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pub mod coverage;
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mod generic_graph;
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pub mod generic_graphviz;
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mod graph_cyclic_cache;
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pub mod graphviz;
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pub mod interpret;
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pub mod mono;
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pub mod patch;
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mod predecessors;
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pub mod pretty;
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mod query;
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pub mod spanview;
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mod syntax;
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pub use syntax::*;
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mod switch_sources;
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pub mod tcx;
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pub mod terminator;
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pub use terminator::*;
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@ -1,78 +0,0 @@
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//! Lazily compute the reverse control-flow graph for the MIR.
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use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
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use rustc_data_structures::sync::OnceCell;
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use rustc_index::vec::IndexVec;
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use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
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use smallvec::SmallVec;
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use crate::mir::{BasicBlock, BasicBlockData};
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// Typically 95%+ of basic blocks have 4 or fewer predecessors.
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pub type Predecessors = IndexVec<BasicBlock, SmallVec<[BasicBlock; 4]>>;
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#[derive(Clone, Debug)]
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pub(super) struct PredecessorCache {
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cache: OnceCell<Predecessors>,
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}
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impl PredecessorCache {
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#[inline]
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pub(super) fn new() -> Self {
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PredecessorCache { cache: OnceCell::new() }
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}
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/// Invalidates the predecessor cache.
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#[inline]
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pub(super) fn invalidate(&mut self) {
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// Invalidating the predecessor cache requires mutating the MIR, which in turn requires a
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// unique reference (`&mut`) to the `mir::Body`. Because of this, we can assume that all
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// callers of `invalidate` have a unique reference to the MIR and thus to the predecessor
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// cache. This means we never need to do synchronization when `invalidate` is called, we can
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// simply reinitialize the `OnceCell`.
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self.cache = OnceCell::new();
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}
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/// Returns the predecessor graph for this MIR.
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#[inline]
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pub(super) fn compute(
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&self,
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basic_blocks: &IndexVec<BasicBlock, BasicBlockData<'_>>,
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) -> &Predecessors {
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self.cache.get_or_init(|| {
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let mut preds = IndexVec::from_elem(SmallVec::new(), basic_blocks);
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for (bb, data) in basic_blocks.iter_enumerated() {
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if let Some(term) = &data.terminator {
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for succ in term.successors() {
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preds[succ].push(bb);
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}
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}
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}
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preds
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})
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}
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}
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impl<S: Encoder> Encodable<S> for PredecessorCache {
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#[inline]
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fn encode(&self, _s: &mut S) {}
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}
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impl<D: Decoder> Decodable<D> for PredecessorCache {
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#[inline]
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fn decode(_: &mut D) -> Self {
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Self::new()
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}
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}
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impl<CTX> HashStable<CTX> for PredecessorCache {
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#[inline]
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fn hash_stable(&self, _: &mut CTX, _: &mut StableHasher) {
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// do nothing
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}
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}
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TrivialTypeTraversalAndLiftImpls! {
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PredecessorCache,
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}
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@ -1,78 +0,0 @@
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//! Lazily compute the inverse of each `SwitchInt`'s switch targets. Modeled after
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//! `Predecessors`/`PredecessorCache`.
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use rustc_data_structures::fx::FxHashMap;
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use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
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use rustc_data_structures::sync::OnceCell;
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use rustc_index::vec::IndexVec;
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use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
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use smallvec::SmallVec;
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use crate::mir::{BasicBlock, BasicBlockData, Terminator, TerminatorKind};
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pub type SwitchSources = FxHashMap<(BasicBlock, BasicBlock), SmallVec<[Option<u128>; 1]>>;
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#[derive(Clone, Debug)]
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pub(super) struct SwitchSourceCache {
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cache: OnceCell<SwitchSources>,
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}
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impl SwitchSourceCache {
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#[inline]
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pub(super) fn new() -> Self {
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SwitchSourceCache { cache: OnceCell::new() }
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}
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/// Invalidates the switch source cache.
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#[inline]
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pub(super) fn invalidate(&mut self) {
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self.cache = OnceCell::new();
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}
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/// Returns the switch sources for this MIR.
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#[inline]
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pub(super) fn compute(
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&self,
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basic_blocks: &IndexVec<BasicBlock, BasicBlockData<'_>>,
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) -> &SwitchSources {
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self.cache.get_or_init(|| {
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let mut switch_sources: SwitchSources = FxHashMap::default();
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for (bb, data) in basic_blocks.iter_enumerated() {
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if let Some(Terminator {
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kind: TerminatorKind::SwitchInt { targets, .. }, ..
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}) = &data.terminator
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{
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for (value, target) in targets.iter() {
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switch_sources.entry((target, bb)).or_default().push(Some(value));
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}
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switch_sources.entry((targets.otherwise(), bb)).or_default().push(None);
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}
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}
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switch_sources
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})
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}
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}
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impl<S: Encoder> Encodable<S> for SwitchSourceCache {
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#[inline]
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fn encode(&self, _s: &mut S) {}
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}
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impl<D: Decoder> Decodable<D> for SwitchSourceCache {
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#[inline]
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fn decode(_: &mut D) -> Self {
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Self::new()
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}
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}
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impl<CTX> HashStable<CTX> for SwitchSourceCache {
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#[inline]
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fn hash_stable(&self, _: &mut CTX, _: &mut StableHasher) {
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// do nothing
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}
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}
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TrivialTypeTraversalAndLiftImpls! {
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SwitchSourceCache,
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}
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@ -1,7 +1,4 @@
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use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
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use rustc_data_structures::sync::OnceCell;
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use rustc_index::bit_set::BitSet;
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use rustc_serialize::{Decodable, Decoder, Encodable, Encoder};
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use super::*;
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@ -339,50 +336,3 @@ pub fn reverse_postorder<'a, 'tcx>(body: &'a Body<'tcx>) -> ReversePostorderIter
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let len = blocks.len();
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ReversePostorderIter { body, blocks, idx: len }
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}
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#[derive(Clone, Debug)]
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pub(super) struct PostorderCache {
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cache: OnceCell<Vec<BasicBlock>>,
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}
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impl PostorderCache {
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#[inline]
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pub(super) fn new() -> Self {
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PostorderCache { cache: OnceCell::new() }
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}
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/// Invalidates the postorder cache.
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#[inline]
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pub(super) fn invalidate(&mut self) {
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self.cache = OnceCell::new();
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}
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/// Returns the `&[BasicBlocks]` represents the postorder graph for this MIR.
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#[inline]
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pub(super) fn compute(&self, body: &IndexVec<BasicBlock, BasicBlockData<'_>>) -> &[BasicBlock] {
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self.cache.get_or_init(|| Postorder::new(body, START_BLOCK).map(|(bb, _)| bb).collect())
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}
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}
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impl<S: Encoder> Encodable<S> for PostorderCache {
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#[inline]
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fn encode(&self, _s: &mut S) {}
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}
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impl<D: Decoder> Decodable<D> for PostorderCache {
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#[inline]
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fn decode(_: &mut D) -> Self {
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Self::new()
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}
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}
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impl<CTX> HashStable<CTX> for PostorderCache {
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#[inline]
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fn hash_stable(&self, _: &mut CTX, _: &mut StableHasher) {
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// do nothing
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}
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}
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TrivialTypeTraversalAndLiftImpls! {
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PostorderCache,
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}
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