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Add MIPS asm! support
This patch also: * Add soft-float supports: only f32 * zero-extend i8/i16 to i32 because MIPS only supports register-length arithmetic. * Update table in asm! chapter in unstable book.
This commit is contained in:
Lzu Tao
parent
5fae56971d
commit
9000710959
@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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InlineAsmArch::Nvptx64 => {}
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InlineAsmArch::Hexagon => {}
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InlineAsmArch::Mips => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
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@ -551,6 +554,7 @@ fn modifier_to_llvm(
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}
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}
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InlineAsmRegClass::Hexagon(_) => None,
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InlineAsmRegClass::Mips(_) => None,
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InlineAsmRegClass::Nvptx(_) => None,
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
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| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
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@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
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cx.type_vector(cx.type_i64(), 2)
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}
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
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@ -700,6 +706,12 @@ fn llvm_fixup_input(
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value
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
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_ => value,
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},
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_ => value,
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}
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}
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@ -768,6 +780,13 @@ fn llvm_fixup_output(
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value
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
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Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
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_ => value,
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},
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_ => value,
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}
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}
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@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
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layout.llvm_type(cx)
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
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Primitive::F32 => cx.type_i32(),
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_ => layout.llvm_type(cx),
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},
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_ => layout.llvm_type(cx),
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}
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}
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132
compiler/rustc_target/src/asm/mips.rs
Normal file
132
compiler/rustc_target/src/asm/mips.rs
Normal file
@ -0,0 +1,132 @@
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use super::{InlineAsmArch, InlineAsmType};
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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def_reg_class! {
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Mips MipsInlineAsmRegClass {
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reg,
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freg,
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}
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}
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impl MipsInlineAsmRegClass {
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pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
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&[]
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}
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pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
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None
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}
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pub fn suggest_modifier(
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self,
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_arch: InlineAsmArch,
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_ty: InlineAsmType,
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) -> Option<(char, &'static str)> {
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None
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}
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pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
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None
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}
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pub fn supported_types(
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self,
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_arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<&'static str>)] {
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match self {
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Self::reg => types! { _: I8, I16, I32, F32; },
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Self::freg => types! { _: F32; },
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}
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}
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}
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// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
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def_regs! {
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Mips MipsInlineAsmReg MipsInlineAsmRegClass {
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v0: reg = ["$2", "$v0"],
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v1: reg = ["$3", "$v1"],
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a0: reg = ["$4", "$a0"],
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a1: reg = ["$5", "$a1"],
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a2: reg = ["$6", "$a2"],
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a3: reg = ["$7", "$a3"],
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// FIXME: Reserve $t0, $t1 if in mips16 mode.
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t0: reg = ["$8", "$t0"],
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t1: reg = ["$9", "$t1"],
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t2: reg = ["$10", "$t2"],
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t3: reg = ["$11", "$t3"],
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t4: reg = ["$12", "$t4"],
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t5: reg = ["$13", "$t5"],
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t6: reg = ["$14", "$t6"],
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t7: reg = ["$15", "$t7"],
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s0: reg = ["$16", "$s0"],
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s1: reg = ["$17", "$s1"],
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s2: reg = ["$18", "$s2"],
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s3: reg = ["$19", "$s3"],
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s4: reg = ["$20", "$s4"],
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s5: reg = ["$21", "$s5"],
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s6: reg = ["$22", "$s6"],
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s7: reg = ["$23", "$s7"],
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t8: reg = ["$24", "$t8"],
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t9: reg = ["$25", "$t9"],
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f0: freg = ["$f0"],
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f1: freg = ["$f1"],
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f2: freg = ["$f2"],
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f3: freg = ["$f3"],
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f4: freg = ["$f4"],
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f5: freg = ["$f5"],
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f6: freg = ["$f6"],
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f7: freg = ["$f7"],
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f8: freg = ["$f8"],
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f9: freg = ["$f9"],
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f10: freg = ["$f10"],
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f11: freg = ["$f11"],
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f12: freg = ["$f12"],
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f13: freg = ["$f13"],
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f14: freg = ["$f14"],
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f15: freg = ["$f15"],
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f16: freg = ["$f16"],
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f17: freg = ["$f17"],
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f18: freg = ["$f18"],
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f19: freg = ["$f19"],
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f20: freg = ["$f20"],
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f21: freg = ["$f21"],
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f22: freg = ["$f22"],
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f23: freg = ["$f23"],
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f24: freg = ["$f24"],
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f25: freg = ["$f25"],
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f26: freg = ["$f26"],
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f27: freg = ["$f27"],
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f28: freg = ["$f28"],
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f29: freg = ["$f29"],
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f30: freg = ["$f30"],
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f31: freg = ["$f31"],
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#error = ["$0", "$zero"] =>
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"constant zero cannot be used as an operand for inline asm",
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#error = ["$1", "$at"] =>
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"reserved for assembler (Assembler Temp)",
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#error = ["$26", "$k0"] =>
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"OS-reserved register cannot be used as an operand for inline asm",
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#error = ["$27", "$k1"] =>
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"OS-reserved register cannot be used as an operand for inline asm",
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#error = ["$28", "$gp"] =>
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"the global pointer cannot be used as an operand for inline asm",
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#error = ["$29", "$sp"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["$30", "$s8", "$fp"] =>
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"the frame pointer cannot be used as an operand for inline asm",
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#error = ["$31", "$ra"] =>
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"the return address register cannot be used as an operand for inline asm",
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}
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}
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impl MipsInlineAsmReg {
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pub fn emit(
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self,
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out: &mut dyn fmt::Write,
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_arch: InlineAsmArch,
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_modifier: Option<char>,
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) -> fmt::Result {
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out.write_str(self.name())
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}
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}
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@ -152,6 +152,7 @@ macro_rules! types {
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mod aarch64;
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mod arm;
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mod hexagon;
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mod mips;
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mod nvptx;
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mod riscv;
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mod x86;
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@ -159,6 +160,7 @@ mod x86;
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pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
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pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
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pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
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pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
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@ -173,6 +175,7 @@ pub enum InlineAsmArch {
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RiscV64,
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Nvptx64,
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Hexagon,
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Mips,
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}
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impl FromStr for InlineAsmArch {
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@ -188,6 +191,7 @@ impl FromStr for InlineAsmArch {
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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"hexagon" => Ok(Self::Hexagon),
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"mips" => Ok(Self::Mips),
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_ => Err(()),
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}
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}
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@ -201,6 +205,7 @@ pub enum InlineAsmReg {
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RiscV(RiscVInlineAsmReg),
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Nvptx(NvptxInlineAsmReg),
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Hexagon(HexagonInlineAsmReg),
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Mips(MipsInlineAsmReg),
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}
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impl InlineAsmReg {
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@ -211,6 +216,7 @@ impl InlineAsmReg {
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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}
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}
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@ -221,6 +227,7 @@ impl InlineAsmReg {
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Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
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Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
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Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
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Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
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}
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}
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@ -252,6 +259,9 @@ impl InlineAsmReg {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Mips => {
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Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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})
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}
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@ -269,6 +279,7 @@ impl InlineAsmReg {
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Self::AArch64(r) => r.emit(out, arch, modifier),
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Self::RiscV(r) => r.emit(out, arch, modifier),
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Self::Hexagon(r) => r.emit(out, arch, modifier),
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Self::Mips(r) => r.emit(out, arch, modifier),
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}
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}
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@ -279,6 +290,7 @@ impl InlineAsmReg {
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Self::AArch64(_) => cb(self),
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Self::RiscV(_) => cb(self),
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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Self::Mips(_) => cb(self),
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}
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}
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}
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@ -291,6 +303,7 @@ pub enum InlineAsmRegClass {
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RiscV(RiscVInlineAsmRegClass),
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Nvptx(NvptxInlineAsmRegClass),
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Hexagon(HexagonInlineAsmRegClass),
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Mips(MipsInlineAsmRegClass),
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}
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impl InlineAsmRegClass {
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@ -302,6 +315,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.name(),
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Self::Nvptx(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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}
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}
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@ -316,6 +330,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
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Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
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}
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}
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@ -337,6 +352,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.suggest_modifier(arch, ty),
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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Self::Hexagon(r) => r.suggest_modifier(arch, ty),
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Self::Mips(r) => r.suggest_modifier(arch, ty),
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}
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}
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@ -354,6 +370,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.default_modifier(arch),
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Self::Nvptx(r) => r.default_modifier(arch),
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Self::Hexagon(r) => r.default_modifier(arch),
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Self::Mips(r) => r.default_modifier(arch),
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}
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}
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@ -370,6 +387,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.supported_types(arch),
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Self::Nvptx(r) => r.supported_types(arch),
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Self::Hexagon(r) => r.supported_types(arch),
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Self::Mips(r) => r.supported_types(arch),
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}
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}
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@ -391,6 +409,7 @@ impl InlineAsmRegClass {
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
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})
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})
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}
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@ -405,6 +424,7 @@ impl InlineAsmRegClass {
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Self::RiscV(r) => r.valid_modifiers(arch),
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Self::Nvptx(r) => r.valid_modifiers(arch),
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Self::Hexagon(r) => r.valid_modifiers(arch),
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Self::Mips(r) => r.valid_modifiers(arch),
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}
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}
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}
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@ -545,5 +565,10 @@ pub fn allocatable_registers(
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hexagon::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Mips => {
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let mut map = mips::regclass_map();
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mips::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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}
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}
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@ -27,6 +27,7 @@ Inline assembly is currently supported on the following architectures:
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- RISC-V
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- NVPTX
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- Hexagon
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- MIPS32
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## Basic usage
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@ -493,6 +494,8 @@ Here is the list of currently supported register classes:
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| ARM | `qreg` | `q[0-15]` | `w` |
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| ARM | `qreg_low8` | `q[0-7]` | `t` |
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| ARM | `qreg_low4` | `q[0-3]` | `x` |
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| MIPS32 | `reg` | `$[2-25]` | `r` |
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| MIPS32 | `freg` | `$f[0-31]` | `f` |
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| NVPTX | `reg16` | None\* | `h` |
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| NVPTX | `reg32` | None\* | `r` |
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| NVPTX | `reg64` | None\* | `l` |
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@ -528,6 +531,8 @@ Each register class has constraints on which value types they can be used with.
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| ARM | `sreg` | `vfp2` | `i32`, `f32` |
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| ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
|
||||
| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
|
||||
| MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
|
||||
| MIPS32 | `freg` | None | `f32` |
|
||||
| NVPTX | `reg16` | None | `i8`, `i16` |
|
||||
| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
|
||||
| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
|
||||
@ -576,6 +581,7 @@ Some registers have multiple names. These are all treated by the compiler as ide
|
||||
| ARM | `r13` | `sp` |
|
||||
| ARM | `r14` | `lr` |
|
||||
| ARM | `r15` | `pc` |
|
||||
| MIPS32 | `$[2-25]` | Please [see the Wikipedia page][mips-regs] |
|
||||
| RISC-V | `x0` | `zero` |
|
||||
| RISC-V | `x1` | `ra` |
|
||||
| RISC-V | `x2` | `sp` |
|
||||
@ -596,12 +602,14 @@ Some registers have multiple names. These are all treated by the compiler as ide
|
||||
| Hexagon | `r30` | `fr` |
|
||||
| Hexagon | `r31` | `lr` |
|
||||
|
||||
[mips-regs]: https://en.wikibooks.org/wiki/MIPS_Assembly/Register_File#Registers
|
||||
|
||||
Some registers cannot be used for input or output operands:
|
||||
|
||||
| Architecture | Unsupported register | Reason |
|
||||
| ------------ | -------------------- | ------ |
|
||||
| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
|
||||
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon) | The frame pointer cannot be used as an input or output. |
|
||||
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS) | The frame pointer cannot be used as an input or output. |
|
||||
| ARM | `r7` or `r11` | On ARM the frame pointer can be either `r7` or `r11` depending on the target. The frame pointer cannot be used as an input or output. |
|
||||
| ARM | `r6` | `r6` is used internally by LLVM as a base pointer and therefore cannot be used as an input or output. |
|
||||
| x86 | `k0` | This is a constant zero register which can't be modified. |
|
||||
@ -610,6 +618,11 @@ Some registers cannot be used for input or output operands:
|
||||
| x86 | `st([0-7])` | x87 registers are not currently supported (but may be in the future). |
|
||||
| AArch64 | `xzr` | This is a constant zero register which can't be modified. |
|
||||
| ARM | `pc` | This is the program counter, not a real register. |
|
||||
| MIPS32 | `$0` or `$zero` | This is a constant zero register which can't be modified. |
|
||||
| MIPS32 | `$1` or `$at` | Reserved for assembler. |
|
||||
| MIPS32 | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
|
||||
| MIPS32 | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
|
||||
| MIPS32 | `$ra` | Return address cannot be used as inputs or outputs. |
|
||||
| RISC-V | `x0` | This is a constant zero register which can't be modified. |
|
||||
| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
|
||||
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
|
||||
@ -657,6 +670,8 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
|
||||
| ARM | `dreg` | None | `d0` | `P` |
|
||||
| ARM | `qreg` | None | `q0` | `q` |
|
||||
| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
|
||||
| MIPS32 | `reg` | None | `$2` | None |
|
||||
| MIPS32 | `freg` | None | `$f0` | None |
|
||||
| NVPTX | `reg16` | None | `rs0` | None |
|
||||
| NVPTX | `reg32` | None | `r0` | None |
|
||||
| NVPTX | `reg64` | None | `rd0` | None |
|
||||
|
||||
191
src/test/assembly/asm/mips-types.rs
Normal file
191
src/test/assembly/asm/mips-types.rs
Normal file
@ -0,0 +1,191 @@
|
||||
// no-system-llvm
|
||||
// assembly-output: emit-asm
|
||||
// compile-flags: --target mips-unknown-linux-gnu
|
||||
// needs-llvm-components: mips
|
||||
|
||||
#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
|
||||
#![crate_type = "rlib"]
|
||||
#![no_core]
|
||||
#![allow(asm_sub_register, non_camel_case_types)]
|
||||
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! asm {
|
||||
() => {};
|
||||
}
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! concat {
|
||||
() => {};
|
||||
}
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! stringify {
|
||||
() => {};
|
||||
}
|
||||
|
||||
#[lang = "sized"]
|
||||
trait Sized {}
|
||||
#[lang = "copy"]
|
||||
trait Copy {}
|
||||
|
||||
type ptr = *const i32;
|
||||
|
||||
impl Copy for i8 {}
|
||||
impl Copy for u8 {}
|
||||
impl Copy for i16 {}
|
||||
impl Copy for i32 {}
|
||||
impl Copy for f32 {}
|
||||
impl Copy for ptr {}
|
||||
extern "C" {
|
||||
fn extern_func();
|
||||
static extern_static: u8;
|
||||
}
|
||||
|
||||
// Hack to avoid function merging
|
||||
extern "Rust" {
|
||||
fn dont_merge(s: &str);
|
||||
}
|
||||
|
||||
macro_rules! check { ($func:ident, $ty:ty, $class:ident) => {
|
||||
#[no_mangle]
|
||||
pub unsafe fn $func(x: $ty) -> $ty {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
let y;
|
||||
asm!("move {}, {}", out($class) y, in($class) x);
|
||||
y
|
||||
}
|
||||
};}
|
||||
|
||||
macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt) => {
|
||||
#[no_mangle]
|
||||
pub unsafe fn $func(x: $ty) -> $ty {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
let y;
|
||||
asm!(concat!("move ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
|
||||
y
|
||||
}
|
||||
};}
|
||||
|
||||
// CHECK-LABEL: sym_static:
|
||||
// CHECK: #APP
|
||||
// CHECK: lw $3, %got(extern_static)
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_static() {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
asm!("la $v1, {}", sym extern_static);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: sym_fn:
|
||||
// CHECK: #APP
|
||||
// CHECK: lw $3, %got(extern_func)
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_fn() {
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
asm!("la $v1, {}", sym extern_func);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: reg_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.s $f{{[0-9]+}}, $f{{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn reg_f32(x: f32) -> f32 {
|
||||
dont_merge("reg_f32");
|
||||
let y;
|
||||
asm!("mov.s {}, {}", out(freg) y, in(freg) x);
|
||||
y
|
||||
}
|
||||
|
||||
// CHECK-LABEL: f0_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: mov.s $f0, $f0
|
||||
// CHECK: #NO_APP
|
||||
#[no_mangle]
|
||||
pub unsafe fn f0_f32(x: f32) -> f32 {
|
||||
dont_merge("f0_f32");
|
||||
let y;
|
||||
asm!("mov.s $f0, $f0", lateout("$f0") y, in("$f0") x);
|
||||
y
|
||||
}
|
||||
|
||||
// CHECK-LABEL: reg_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_ptr, ptr, reg);
|
||||
|
||||
// CHECK-LABEL: reg_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i32, i32, reg);
|
||||
|
||||
// CHECK-LABEL: reg_f32_soft:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_f32_soft, f32, reg);
|
||||
|
||||
// CHECK-LABEL: reg_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i8, i8, reg);
|
||||
|
||||
// CHECK-LABEL: reg_u8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_u8, u8, reg);
|
||||
|
||||
// CHECK-LABEL: reg_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
// CHECK: #NO_APP
|
||||
check!(reg_i16, i16, reg);
|
||||
|
||||
// CHECK-LABEL: t0_ptr:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_ptr, ptr, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_i32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i32, i32, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_f32:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_f32, f32, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_i8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i8, i8, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_u8:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_u8, u8, "$t0");
|
||||
|
||||
// CHECK-LABEL: t0_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(t0_i16, i16, "$t0");
|
||||
|
||||
// CHECK-LABEL: r8_i16:
|
||||
// CHECK: #APP
|
||||
// CHECK: move $8, $8
|
||||
// CHECK: #NO_APP
|
||||
check_reg!(r8_i16, i16, "$8");
|
||||
Loading…
Reference in New Issue
Block a user