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Rollup merge of #130555 - hegza:rv32e, r=workingjubilee

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Initial support for riscv32{e|em|emc}_unknown_none_elf

We have a research prototype of an RV32EMC target and have been successfully running the e, em, emc programs on it. I'm hoping upstreaming this configuration would make the target maintenance slightly easier.

Configuration is based on the respective {i, im, imc} variants. As defined in RISC-V Unprivileged Spec. 20191213, the only change in RVE wrt. RVI is to reduce the number of integer registers to 16 (x0-x15), which also implies

- 2 callee saved registers instead of 12
- 32-bit / 4-byte stack alignment instead of 128 bits / 16 bytes

My initial presumption is that this will not impact how the target is defined for the compiler but only becomes relevant at the runtime level. I am willing to investigate, though.

EDIT: LLVM is now told about the presumed 32-bit stack alignment.

`@Disasm` `@romancardenas`
This commit is contained in:
Matthias Krüger 2024-10-05 19:07:53 +02:00 committed by GitHub
commit 8e31e98ff9
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GPG Key ID: B5690EEEBB952194
13 changed files with 825 additions and 1 deletions
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4
compiler/rustc_target/src/spec/mod.rs
View File

@ -1841,6 +1841,10 @@ supported_targets! {
("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
("riscv32imafc-esp-espidf", riscv32imafc_esp_espidf),
("riscv32e-unknown-none-elf", riscv32e_unknown_none_elf),
("riscv32em-unknown-none-elf", riscv32em_unknown_none_elf),
("riscv32emc-unknown-none-elf", riscv32emc_unknown_none_elf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv32imafc-unknown-none-elf", riscv32imafc_unknown_none_elf),
("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),

34
compiler/rustc_target/src/spec/targets/riscv32e_unknown_none_elf.rs Normal file
View File

@ -0,0 +1,34 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
pub(crate) fn target() -> Target {
Target {
// The below `data_layout` is explicitly specified by the ilp32e ABI in LLVM. See also
// `options.llvm_abiname`.
data_layout: "e-m:e-p:32:32-i64:64-n32-S32".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32E ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),
options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
// The ilp32e ABI specifies the `data_layout`
llvm_abiname: "ilp32e".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}

34
compiler/rustc_target/src/spec/targets/riscv32em_unknown_none_elf.rs Normal file
View File

@ -0,0 +1,34 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
pub(crate) fn target() -> Target {
Target {
// The below `data_layout` is explicitly specified by the ilp32e ABI in LLVM. See also
// `options.llvm_abiname`.
data_layout: "e-m:e-p:32:32-i64:64-n32-S32".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32EM ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),
options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
// The ilp32e ABI specifies the `data_layout`
llvm_abiname: "ilp32e".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+m,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}

34
compiler/rustc_target/src/spec/targets/riscv32emc_unknown_none_elf.rs Normal file
View File

@ -0,0 +1,34 @@
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
pub(crate) fn target() -> Target {
Target {
// The below `data_layout` is explicitly specified by the ilp32e ABI in LLVM. See also
// `options.llvm_abiname`.
data_layout: "e-m:e-p:32:32-i64:64-n32-S32".into(),
llvm_target: "riscv32".into(),
metadata: crate::spec::TargetMetadata {
description: Some("Bare RISC-V (RV32EMC ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(false),
},
pointer_width: 32,
arch: "riscv32".into(),
options: TargetOptions {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),
// The ilp32e ABI specifies the `data_layout`
llvm_abiname: "ilp32e".into(),
max_atomic_width: Some(32),
atomic_cas: false,
features: "+e,+m,+c,+forced-atomics".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
..Default::default()
},
}
}

3
src/bootstrap/src/core/sanity.rs
View File

@ -37,6 +37,9 @@ pub struct Finder {
const STAGE0_MISSING_TARGETS: &[&str] = &[
// just a dummy comment so the list doesn't get onelined
"armv7-rtems-eabihf",
"riscv32e-unknown-none-elf",
"riscv32em-unknown-none-elf",
"riscv32emc-unknown-none-elf",
];
/// Minimum version threshold for libstdc++ required when using prebuilt LLVM

3
src/doc/rustc/src/platform-support.md
View File

@ -413,5 +413,8 @@ target | std | host | notes
[`riscv32imafc-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 32bit with NuttX
[`riscv64imac-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 64bit with NuttX
[`riscv64gc-unknown-nuttx-elf`](platform-support/nuttx.md) | * | | RISC-V 64bit with NuttX
[`riscv32e-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32E ISA)
[`riscv32em-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32EM ISA)
[`riscv32emc-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32EMC ISA)
[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

2
src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md
View File

@ -35,4 +35,4 @@ Rust test-suite on this target.
## Cross-compilation toolchains and C code
This target supports C code. If interlinking with C or C++, you may need to use
`riscv64-unknown-elf-gcc` as a linker instead of `rust-lld`.
`riscv32-unknown-elf-gcc` as a linker instead of `rust-lld`.

30
src/doc/rustc/src/platform-support/riscv32e-unknown-none-elf.md Normal file
View File

@ -0,0 +1,30 @@
# `riscv32{e,em,emc}-unknown-none-elf`
**Tier: 3**
Bare-metal target for RISC-V CPUs with the RV32E, RV32EM and RV32EMC ISAs.
## Target maintainers
* Henri Lunnikivi, <henri.lunnikivi@gmail.com>, [@hegza](https://github.com/hegza)
## Requirements
The target is cross-compiled, and uses static linking. No external toolchain is
required and the default `rust-lld` linker works, but you must specify a linker
script.
## Building the target
This target is included in Rust and can be installed via `rustup`.
## Testing
This is a cross-compiled `no-std` target, which must be run either in a
simulator or by programming them onto suitable hardware. It is not possible to
run the Rust test-suite on this target.
## Cross-compilation toolchains and C code
This target supports C code. If interlinking with C or C++, you may need to use
`riscv32-unknown-elf-gcc` as a linker instead of `rust-lld`.

9
tests/assembly/targets/targets-elf.rs
View File

@ -375,6 +375,15 @@
//@ revisions: riscv32_wrs_vxworks
//@ [riscv32_wrs_vxworks] compile-flags: --target riscv32-wrs-vxworks
//@ [riscv32_wrs_vxworks] needs-llvm-components: riscv
//@ revisions: riscv32e_unknown_none_elf
//@ [riscv32e_unknown_none_elf] compile-flags: --target riscv32e-unknown-none-elf
//@ [riscv32e_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32em_unknown_none_elf
//@ [riscv32em_unknown_none_elf] compile-flags: --target riscv32em-unknown-none-elf
//@ [riscv32em_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32emc_unknown_none_elf
//@ [riscv32emc_unknown_none_elf] compile-flags: --target riscv32emc-unknown-none-elf
//@ [riscv32emc_unknown_none_elf] needs-llvm-components: riscv
//@ revisions: riscv32gc_unknown_linux_gnu
//@ [riscv32gc_unknown_linux_gnu] compile-flags: --target riscv32gc-unknown-linux-gnu
//@ [riscv32gc_unknown_linux_gnu] needs-llvm-components: riscv

194
tests/ui/abi/riscv32e-registers.riscv32e.stderr Normal file
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@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

194
tests/ui/abi/riscv32e-registers.riscv32em.stderr Normal file
View File

@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

194
tests/ui/abi/riscv32e-registers.riscv32emc.stderr Normal file
View File

@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

91
tests/ui/abi/riscv32e-registers.rs Normal file
View File

@ -0,0 +1,91 @@
// Test that loads into registers x16..=x31 are never generated for riscv32{e,em,emc} targets
//
//@ build-fail
//@ revisions: riscv32e riscv32em riscv32emc
//
//@ compile-flags: --crate-type=rlib
//@ [riscv32e] needs-llvm-components: riscv
//@ [riscv32e] compile-flags: --target=riscv32e-unknown-none-elf
//@ [riscv32em] needs-llvm-components: riscv
//@ [riscv32em] compile-flags: --target=riscv32em-unknown-none-elf
//@ [riscv32emc] needs-llvm-components: riscv
//@ [riscv32emc] compile-flags: --target=riscv32emc-unknown-none-elf
#![no_core]
#![feature(no_core, lang_items, rustc_attrs)]
#[rustc_builtin_macro]
macro_rules! asm {
() => {};
}
#[lang = "sized"]
trait Sized {}
// Verify registers x1..=x15 are addressable on riscv32e, but registers x16..=x31 are not
#[no_mangle]
pub unsafe fn registers() {
asm!("li x1, 0");
asm!("li x2, 0");
asm!("li x3, 0");
asm!("li x4, 0");
asm!("li x5, 0");
asm!("li x6, 0");
asm!("li x7, 0");
asm!("li x8, 0");
asm!("li x9, 0");
asm!("li x10, 0");
asm!("li x11, 0");
asm!("li x12, 0");
asm!("li x13, 0");
asm!("li x14, 0");
asm!("li x15, 0");
asm!("li x16, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x17, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x18, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x19, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x20, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x21, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x22, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x23, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x24, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x25, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x26, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x27, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x28, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x29, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x30, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x31, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
}