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Add initial asm!() support for hexagon
GPRs only
This commit is contained in:
parent
bb8674837a
commit
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@ -374,7 +374,7 @@ options := "options(" option *["," option] [","] ")"
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asm := "asm!(" format_string *("," [ident "="] operand) ["," options] [","] ")"
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```
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The macro will initially be supported only on ARM, AArch64, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
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The macro will initially be supported only on ARM, AArch64, Hexagon, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
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[format-syntax]: https://doc.rust-lang.org/std/fmt/#syntax
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@ -386,7 +386,7 @@ As with format strings, named arguments must appear after positional arguments.
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The exact assembly code syntax is target-specific and opaque to the compiler except for the way operands are substituted into the template string to form the code passed to the assembler.
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The 4 targets specified in this RFC (x86, ARM, AArch64, RISC-V) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
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The 5 targets specified in this RFC (x86, ARM, AArch64, RISC-V, Hexagon) all use the assembly code syntax of the GNU assembler (GAS). On x86, the `.intel_syntax noprefix` mode of GAS is used by default. On ARM, the `.syntax unified` mode is used. These targets impose an additional restriction on the assembly code: any assembler state (e.g. the current section which can be changed with `.section`) must be restored to its original value at the end of the asm string. Assembly code that does not conform to the GAS syntax will result in assembler-specific behavior.
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[rfc-2795]: https://github.com/rust-lang/rfcs/pull/2795
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@ -473,6 +473,7 @@ Here is the list of currently supported register classes:
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| NVPTX | `reg64` | None\* | `l` |
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| RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
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| RISC-V | `freg` | `f[0-31]` | `f` |
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| Hexagon | `reg` | `r[0-28]` | `r` |
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> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
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>
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@ -507,6 +508,7 @@ Each register class has constraints on which value types they can be used with.
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| RISC-V64 | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| RISC-V | `freg` | `f` | `f32` |
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| RISC-V | `freg` | `d` | `f64` |
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| Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` |
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> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
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@ -563,13 +565,16 @@ Some registers have multiple names. These are all treated by the compiler as ide
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| RISC-V | `f[10-17]` | `fa[0-7]` |
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| RISC-V | `f[18-27]` | `fs[2-11]` |
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| RISC-V | `f[28-31]` | `ft[8-11]` |
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| Hexagon | `r29` | `sp` |
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| Hexagon | `r30` | `fr` |
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| Hexagon | `r31` | `lr` |
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Some registers cannot be used for input or output operands:
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| Architecture | Unsupported register | Reason |
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| ------------ | -------------------- | ------ |
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| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
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| All | `bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V) | The frame pointer cannot be used as an input or output. |
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| All | `bp` (x86), `r11` (ARM), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon) | The frame pointer cannot be used as an input or output. |
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| x86 | `k0` | This is a constant zero register which can't be modified. |
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| x86 | `ip` | This is the program counter, not a real register. |
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| x86 | `mm[0-7]` | MMX registers are not currently supported (but may be in the future). |
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@ -578,6 +583,7 @@ Some registers cannot be used for input or output operands:
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| ARM | `pc` | This is the program counter, not a real register. |
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| RISC-V | `x0` | This is a constant zero register which can't be modified. |
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| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
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| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
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## Template modifiers
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@ -623,6 +629,7 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
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| NVPTX | `reg64` | None | `rd0` | None |
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| RISC-V | `reg` | None | `x1` | None |
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| RISC-V | `freg` | None | `f0` | None |
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| Hexagon | `reg` | None | `r0` | None |
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> Notes:
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> - on ARM `e` / `f`: this prints the low or high doubleword register name of a NEON quad (128-bit) register.
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@ -255,6 +255,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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InlineAsmArch::Nvptx64 => {}
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InlineAsmArch::Hexagon => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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@ -427,6 +428,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass) -> String {
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => "x",
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
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@ -472,6 +474,7 @@ fn modifier_to_llvm(
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modifier
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}
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}
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InlineAsmRegClass::Hexagon(_) => None,
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InlineAsmRegClass::Nvptx(_) => None,
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InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
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| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
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@ -523,6 +526,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
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cx.type_vector(cx.type_i64(), 2)
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}
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InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
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InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
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93
src/librustc_target/asm/hexagon.rs
Normal file
93
src/librustc_target/asm/hexagon.rs
Normal file
@ -0,0 +1,93 @@
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use super::{InlineAsmArch, InlineAsmType};
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use rustc_macros::HashStable_Generic;
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use std::fmt;
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def_reg_class! {
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Hexagon HexagonInlineAsmRegClass {
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reg,
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}
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}
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impl HexagonInlineAsmRegClass {
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pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
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&[]
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}
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pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
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None
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}
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pub fn suggest_modifier(
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self,
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_arch: InlineAsmArch,
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_ty: InlineAsmType,
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) -> Option<(char, &'static str)> {
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None
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}
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pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
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None
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}
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pub fn supported_types(
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self,
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_arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<&'static str>)] {
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match self {
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Self::reg => types! { _: I8, I16, I32, F32; },
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}
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}
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}
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def_regs! {
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Hexagon HexagonInlineAsmReg HexagonInlineAsmRegClass {
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r0: reg = ["r0"],
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r1: reg = ["r1"],
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r2: reg = ["r2"],
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r3: reg = ["r3"],
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r4: reg = ["r4"],
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r5: reg = ["r5"],
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r6: reg = ["r6"],
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r7: reg = ["r7"],
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r8: reg = ["r8"],
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r9: reg = ["r9"],
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r10: reg = ["r10"],
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r11: reg = ["r11"],
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r12: reg = ["r12"],
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r13: reg = ["r13"],
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r14: reg = ["r14"],
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r15: reg = ["r15"],
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r16: reg = ["r16"],
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r17: reg = ["r17"],
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r18: reg = ["r18"],
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r19: reg = ["r19"],
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r20: reg = ["r20"],
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r21: reg = ["r21"],
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r22: reg = ["r22"],
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r23: reg = ["r23"],
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r24: reg = ["r24"],
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r25: reg = ["r25"],
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r26: reg = ["r26"],
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r27: reg = ["r27"],
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r28: reg = ["r28"],
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#error = ["r29", "sp"] =>
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"the stack pointer cannot be used as an operand for inline asm",
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#error = ["r30", "fr"] =>
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"the frame register cannot be used as an operand for inline asm",
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#error = ["r31", "lr"] =>
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"the link register cannot be used as an operand for inline asm",
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}
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}
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impl HexagonInlineAsmReg {
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pub fn emit(
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self,
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out: &mut dyn fmt::Write,
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_arch: InlineAsmArch,
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_modifier: Option<char>,
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) -> fmt::Result {
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out.write_str(self.name())
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}
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pub fn overlapping_regs(self, mut _cb: impl FnMut(HexagonInlineAsmReg)) {}
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}
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@ -148,12 +148,14 @@ macro_rules! types {
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mod aarch64;
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mod arm;
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mod hexagon;
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mod nvptx;
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mod riscv;
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mod x86;
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pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
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pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
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pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
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@ -167,6 +169,7 @@ pub enum InlineAsmArch {
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RiscV32,
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RiscV64,
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Nvptx64,
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Hexagon,
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}
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impl FromStr for InlineAsmArch {
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@ -181,6 +184,7 @@ impl FromStr for InlineAsmArch {
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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"hexagon" => Ok(Self::Hexagon),
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_ => Err(()),
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}
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}
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@ -203,6 +207,7 @@ pub enum InlineAsmReg {
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AArch64(AArch64InlineAsmReg),
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RiscV(RiscVInlineAsmReg),
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Nvptx(NvptxInlineAsmReg),
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Hexagon(HexagonInlineAsmReg),
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}
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impl InlineAsmReg {
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@ -212,6 +217,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.name(),
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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}
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}
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@ -221,6 +227,7 @@ impl InlineAsmReg {
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Self::Arm(r) => InlineAsmRegClass::Arm(r.reg_class()),
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Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
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Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
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Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
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}
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}
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@ -246,6 +253,9 @@ impl InlineAsmReg {
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InlineAsmArch::Nvptx64 => {
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
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}
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, &name)?)
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}
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})
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}
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@ -262,6 +272,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.emit(out, arch, modifier),
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Self::AArch64(r) => r.emit(out, arch, modifier),
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Self::RiscV(r) => r.emit(out, arch, modifier),
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Self::Hexagon(r) => r.emit(out, arch, modifier),
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}
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}
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@ -271,6 +282,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.overlapping_regs(|r| cb(Self::Arm(r))),
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Self::AArch64(_) => cb(self),
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Self::RiscV(_) => cb(self),
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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}
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}
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}
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@ -292,6 +304,7 @@ pub enum InlineAsmRegClass {
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AArch64(AArch64InlineAsmRegClass),
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RiscV(RiscVInlineAsmRegClass),
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Nvptx(NvptxInlineAsmRegClass),
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Hexagon(HexagonInlineAsmRegClass),
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}
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impl InlineAsmRegClass {
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@ -302,6 +315,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Nvptx(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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}
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}
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@ -315,6 +329,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
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Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
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}
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}
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@ -335,6 +350,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.suggest_modifier(arch, ty),
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Self::RiscV(r) => r.suggest_modifier(arch, ty),
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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Self::Hexagon(r) => r.suggest_modifier(arch, ty),
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}
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}
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@ -351,6 +367,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.default_modifier(arch),
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Self::RiscV(r) => r.default_modifier(arch),
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Self::Nvptx(r) => r.default_modifier(arch),
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Self::Hexagon(r) => r.default_modifier(arch),
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}
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}
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@ -366,6 +383,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.supported_types(arch),
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Self::RiscV(r) => r.supported_types(arch),
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Self::Nvptx(r) => r.supported_types(arch),
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Self::Hexagon(r) => r.supported_types(arch),
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}
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}
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@ -384,6 +402,9 @@ impl InlineAsmRegClass {
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Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
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}
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})
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})
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}
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@ -397,6 +418,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.valid_modifiers(arch),
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Self::RiscV(r) => r.valid_modifiers(arch),
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Self::Nvptx(r) => r.valid_modifiers(arch),
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Self::Hexagon(r) => r.valid_modifiers(arch),
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}
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}
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}
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@ -541,5 +563,10 @@ pub fn allocatable_registers(
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nvptx::fill_reg_map(arch, has_feature, &mut map);
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map
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}
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InlineAsmArch::Hexagon => {
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let mut map = hexagon::regclass_map();
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hexagon::fill_reg_map(arch, has_feature, &mut map);
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map
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}
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}
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}
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130
src/test/assembly/asm/hexagon-types.rs
Normal file
130
src/test/assembly/asm/hexagon-types.rs
Normal file
@ -0,0 +1,130 @@
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// no-system-llvm
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// assembly-output: emit-asm
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// compile-flags: --target hexagon-unknown-linux-musl
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#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
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#![crate_type = "rlib"]
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#![no_core]
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#![allow(asm_sub_register, non_camel_case_types)]
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#[rustc_builtin_macro]
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macro_rules! asm {
|
||||
() => {};
|
||||
}
|
||||
#[rustc_builtin_macro]
|
||||
macro_rules! stringify {
|
||||
() => {};
|
||||
}
|
||||
|
||||
#[lang = "sized"]
|
||||
trait Sized {}
|
||||
#[lang = "copy"]
|
||||
trait Copy {}
|
||||
|
||||
type ptr = *const i32;
|
||||
|
||||
impl Copy for i8 {}
|
||||
impl Copy for i16 {}
|
||||
impl Copy for i32 {}
|
||||
impl Copy for f32 {}
|
||||
impl Copy for ptr {}
|
||||
extern "C" {
|
||||
fn extern_func();
|
||||
static extern_static: u8;
|
||||
}
|
||||
|
||||
macro_rules! check {
|
||||
($func:ident $ty:ident $class:ident) => {
|
||||
#[no_mangle]
|
||||
pub unsafe fn $func(x: $ty) -> $ty {
|
||||
// Hack to avoid function merging
|
||||
extern "Rust" {
|
||||
fn dont_merge(s: &str);
|
||||
}
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
let y;
|
||||
asm!("{} = {}", out($class) y, in($class) x);
|
||||
y
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
// CHECK-LABEL: sym_static:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r0 = #extern_static
|
||||
// CHECK: InlineAsm End
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_static() {
|
||||
// Hack to avoid function merging
|
||||
extern "Rust" {
|
||||
fn dont_merge(s: &str);
|
||||
}
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
asm!("r0 = #{}", sym extern_static);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: sym_fn:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r0 = #extern_func
|
||||
// CHECK: InlineAsm End
|
||||
#[no_mangle]
|
||||
pub unsafe fn sym_fn() {
|
||||
// Hack to avoid function merging
|
||||
extern "Rust" {
|
||||
fn dont_merge(s: &str);
|
||||
}
|
||||
dont_merge(stringify!($func));
|
||||
|
||||
asm!("r0 = #{}", sym extern_func);
|
||||
}
|
||||
|
||||
// This is a test for multi-instruction packets,
|
||||
// which require the escaped braces.
|
||||
//
|
||||
// CHECK-LABEL: packet:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: {
|
||||
// CHECK: r{{[0-9]+}} = r0
|
||||
// CHECK: memw(r1) = r{{[0-9]+}}
|
||||
// CHECK: }
|
||||
// CHECK: InlineAsm End
|
||||
#[no_mangle]
|
||||
pub unsafe fn packet() {
|
||||
let val = 1024;
|
||||
asm!("{{
|
||||
{} = r0
|
||||
memw(r1) = {}
|
||||
}}", out(reg) _, in(reg) &val);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: ptr:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r{{[0-9]+}} = r{{[0-9]+}}
|
||||
// CHECK: InlineAsm End
|
||||
check!(reg_ptr ptr reg);
|
||||
|
||||
// CHECK-LABEL: reg_f32:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r{{[0-9]+}} = r{{[0-9]+}}
|
||||
// CHECK: InlineAsm End
|
||||
check!(reg_f32 f32 reg);
|
||||
|
||||
// CHECK-LABEL: reg_i32:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r{{[0-9]+}} = r{{[0-9]+}}
|
||||
// CHECK: InlineAsm End
|
||||
check!(reg_i32 i32 reg);
|
||||
|
||||
// CHECK-LABEL: reg_i8:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r{{[0-9]+}} = r{{[0-9]+}}
|
||||
// CHECK: InlineAsm End
|
||||
check!(reg_i8 i8 reg);
|
||||
|
||||
// CHECK-LABEL: reg_i16:
|
||||
// CHECK: InlineAsm Start
|
||||
// CHECK: r{{[0-9]+}} = r{{[0-9]+}}
|
||||
// CHECK: InlineAsm End
|
||||
check!(reg_i16 i16 reg);
|
Loading…
Reference in New Issue
Block a user