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Auto merge of #38561 - nagisa:rdrandseed, r=alexcrichton
Add intrinsics & target features for rd{rand,seed} One question is whether or not we want to map feature name `rdrnd` to `rdrand` instead. EDIT: as for use case, I would like to port my rdrand crate from inline assembly to these intrinsics.
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commit
61b93bd811
27
src/etc/platform-intrinsics/x86/rdrand.json
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27
src/etc/platform-intrinsics/x86/rdrand.json
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@ -0,0 +1,27 @@
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{
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"intrinsic_prefix": "_rdrand",
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"llvm_prefix": "llvm.x86.rdrand.",
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"intrinsics": [
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{
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"intrinsic": "16_step",
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"width": ["0"],
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"llvm": "16",
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"ret": "(U16,S32)",
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"args": []
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},
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{
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"intrinsic": "32_step",
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"width": ["0"],
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"llvm": "32",
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"ret": "(U32,S32)",
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"args": []
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},
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{
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"intrinsic": "64_step",
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"width": ["0"],
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"llvm": "64",
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"ret": "(U64,S32)",
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"args": []
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}
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]
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}
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27
src/etc/platform-intrinsics/x86/rdseed.json
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27
src/etc/platform-intrinsics/x86/rdseed.json
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@ -0,0 +1,27 @@
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{
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"intrinsic_prefix": "_rdseed",
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"llvm_prefix": "llvm.x86.rdseed.",
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"intrinsics": [
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{
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"intrinsic": "16_step",
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"width": ["0"],
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"llvm": "16",
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"ret": "(U16,S32)",
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"args": []
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},
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{
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"intrinsic": "32_step",
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"width": ["0"],
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"llvm": "32",
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"ret": "(U32,S32)",
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"args": []
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},
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{
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"intrinsic": "64_step",
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"width": ["0"],
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"llvm": "64",
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"ret": "(U64,S32)",
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"args": []
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}
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]
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}
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@ -25,7 +25,7 @@ const ARM_WHITELIST: &'static [&'static str] = &["neon\0", "vfp2\0", "vfp3\0", "
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const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bmi2\0", "sse\0",
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"sse2\0", "sse3\0", "sse4.1\0", "sse4.2\0",
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"ssse3\0", "tbm\0", "lzcnt\0", "popcnt\0",
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"sse4a\0"];
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"sse4a\0", "rdrnd\0", "rdseed\0"];
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/// Add `target_feature = "..."` cfgs for a variety of platform
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/// specific features (SSE, NEON etc.).
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@ -872,6 +872,36 @@ pub fn find(name: &str) -> Option<Intrinsic> {
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output: &::F64x4,
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definition: Named("llvm.x86.fma.vfnmsub.pd.256")
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},
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"_rdrand16_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdrand.16")
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},
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"_rdrand32_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdrand.32")
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},
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"_rdrand64_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdrand.64")
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},
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"_rdseed16_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdseed.16")
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},
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"_rdseed32_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdseed.32")
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},
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"_rdseed64_step" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
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output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG },
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definition: Named("llvm.x86.rdseed.64")
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},
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"_mm_adds_epi8" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I8x16,
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