From 48be303272e8eb620665b73a7bd87cdb6508f6f1 Mon Sep 17 00:00:00 2001 From: Zachary Yedidia Date: Sun, 2 Apr 2023 07:30:42 -0700 Subject: [PATCH] Add riscv relax target feature --- compiler/rustc_codegen_ssa/src/target_features.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index 754b085f1a8..611dd3d1cd1 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -251,6 +251,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option)] = &[ ("e", Some(sym::riscv_target_feature)), ("f", Some(sym::riscv_target_feature)), ("m", Some(sym::riscv_target_feature)), + ("relax", Some(sym::riscv_target_feature)), ("v", Some(sym::riscv_target_feature)), ("zba", Some(sym::riscv_target_feature)), ("zbb", Some(sym::riscv_target_feature)),