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Rollup merge of #101495 - bjorn3:pause-no-sse2, r=Mark-Simulacrum

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Compile spin_loop_hint as pause on x86 even without sse2 enabled

The x86 `pause` instruction was introduced with sse2, but because it is encoded as `rep nop`, it works just fine on cpu's without sse2 support. It just doesn't do anything.
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Guillaume Gomez 2022-09-09 15:36:36 +02:00 committed by GitHub
commit 3ec332fc82
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1 changed files with 8 additions and 11 deletions
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19
library/core/src/hint.rs
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@ -160,19 +160,16 @@ pub const unsafe fn unreachable_unchecked() -> ! {
#[inline] #[inline]
#[stable(feature = "renamed_spin_loop", since = "1.49.0")] #[stable(feature = "renamed_spin_loop", since = "1.49.0")]
pub fn spin_loop() { pub fn spin_loop() {
#[cfg(all(any(target_arch = "x86", target_arch = "x86_64"), target_feature = "sse2"))] #[cfg(target_arch = "x86")]
{ {
#[cfg(target_arch = "x86")] // SAFETY: the `cfg` attr ensures that we only execute this on x86 targets.
{ unsafe { crate::arch::x86::_mm_pause() };
// SAFETY: the `cfg` attr ensures that we only execute this on x86 targets. }
unsafe { crate::arch::x86::_mm_pause() };
}
#[cfg(target_arch = "x86_64")] #[cfg(target_arch = "x86_64")]
{ {
// SAFETY: the `cfg` attr ensures that we only execute this on x86_64 targets. // SAFETY: the `cfg` attr ensures that we only execute this on x86_64 targets.
unsafe { crate::arch::x86_64::_mm_pause() }; unsafe { crate::arch::x86_64::_mm_pause() };
}
} }
// RISC-V platform spin loop hint implementation // RISC-V platform spin loop hint implementation