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Add UI test to verify invalid loads are not generated

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This commit is contained in:
Henri Lunnikivi 2024-10-04 18:20:53 +03:00 committed by Henri Lunnikivi
parent fe658e1fe4
commit 346afc7017
4 changed files with 673 additions and 0 deletions
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194
tests/ui/abi/riscv32e-registers.riscv32e.stderr Normal file
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@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

194
tests/ui/abi/riscv32e-registers.riscv32em.stderr Normal file
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@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

194
tests/ui/abi/riscv32e-registers.riscv32emc.stderr Normal file
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@ -0,0 +1,194 @@
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:43:11
|
LL | asm!("li x16, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x16, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:46:11
|
LL | asm!("li x17, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x17, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:49:11
|
LL | asm!("li x18, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x18, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:52:11
|
LL | asm!("li x19, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x19, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:55:11
|
LL | asm!("li x20, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x20, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:58:11
|
LL | asm!("li x21, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x21, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:61:11
|
LL | asm!("li x22, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x22, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:64:11
|
LL | asm!("li x23, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x23, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:67:11
|
LL | asm!("li x24, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x24, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:70:11
|
LL | asm!("li x25, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x25, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:73:11
|
LL | asm!("li x26, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x26, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:76:11
|
LL | asm!("li x27, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x27, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:79:11
|
LL | asm!("li x28, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x28, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:82:11
|
LL | asm!("li x29, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x29, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:85:11
|
LL | asm!("li x30, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x30, 0
| ^
error: invalid operand for instruction
--> $DIR/riscv32e-registers.rs:88:11
|
LL | asm!("li x31, 0");
| ^
|
note: instantiated into assembly here
--> <inline asm>:1:5
|
LL | li x31, 0
| ^
error: aborting due to 16 previous errors

91
tests/ui/abi/riscv32e-registers.rs Normal file
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@ -0,0 +1,91 @@
// Test that loads into registers x16..=x31 are never generated for riscv32{e,em,emc} targets
//
//@ build-fail
//@ revisions: riscv32e riscv32em riscv32emc
//
//@ compile-flags: --crate-type=rlib
//@ [riscv32e] needs-llvm-components: riscv
//@ [riscv32e] compile-flags: --target=riscv32e-unknown-none-elf
//@ [riscv32em] needs-llvm-components: riscv
//@ [riscv32em] compile-flags: --target=riscv32em-unknown-none-elf
//@ [riscv32emc] needs-llvm-components: riscv
//@ [riscv32emc] compile-flags: --target=riscv32emc-unknown-none-elf
#![no_core]
#![feature(no_core, lang_items, rustc_attrs)]
#[rustc_builtin_macro]
macro_rules! asm {
() => {};
}
#[lang = "sized"]
trait Sized {}
// Verify registers x1..=x15 are addressable on riscv32e, but registers x16..=x31 are not
#[no_mangle]
pub unsafe fn registers() {
asm!("li x1, 0");
asm!("li x2, 0");
asm!("li x3, 0");
asm!("li x4, 0");
asm!("li x5, 0");
asm!("li x6, 0");
asm!("li x7, 0");
asm!("li x8, 0");
asm!("li x9, 0");
asm!("li x10, 0");
asm!("li x11, 0");
asm!("li x12, 0");
asm!("li x13, 0");
asm!("li x14, 0");
asm!("li x15, 0");
asm!("li x16, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x17, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x18, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x19, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x20, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x21, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x22, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x23, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x24, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x25, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x26, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x27, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x28, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x29, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x30, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
asm!("li x31, 0");
//~^ ERROR invalid operand for instruction
//~| NOTE instantiated into assembly here
}