From 1a0ba0117794bb80e540bb449c4109b8f20060c1 Mon Sep 17 00:00:00 2001 From: Chris Copeland Date: Thu, 12 Sep 2024 23:41:39 -0700 Subject: [PATCH] Fix target-cpu fpu features on Armv8-R. This is a follow-up to #123159, but applied to Armv8-R. This required https://github.com/llvm/llvm-project/pull/88287 to work properly. Now that this change exists in rustc's llvm, we can fix Armv8-R's default fpu features. In Armv8-R's case, the default features from LLVM for floating-point are sufficient, because there is no integer-only variant of this architecture. --- .../src/spec/targets/armv8r_none_eabihf.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs index 042a9a14071..762084291a6 100644 --- a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs @@ -21,16 +21,16 @@ pub(crate) fn target() -> Target { linker: Some("rust-lld".into()), relocation_model: RelocModel::Static, panic_strategy: PanicStrategy::Abort, - // The Cortex-R52 has two variants with respect to floating-point support: - // 1. fp-armv8, SP-only, with 16 DP (32 SP) registers - // 2. neon-fp-armv8, SP+DP, with 32 DP registers - // Use the lesser of these two options as the default, as it will produce code - // compatible with either variant. + // Armv8-R requires a minimum set of floating-point features equivalent to: + // fp-armv8, SP-only, with 16 DP (32 SP) registers + // LLVM defines Armv8-R to include these features automatically. + // + // The Cortex-R52 supports these default features and optionally includes: + // neon-fp-armv8, SP+DP, with 32 DP registers // // Reference: // Arm Cortex-R52 Processor Technical Reference Manual // - Chapter 15 Advanced SIMD and floating-point support - features: "+fp-armv8,-fp64,-d32".into(), max_atomic_width: Some(64), emit_debug_gdb_scripts: false, // GCC defaults to 8 for arm-none here.