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Rollup merge of #133029 - veluca93:abi-checks-tier3, r=workingjubilee
ABI checks: add support for some tier3 arches, warn on others. Followup to - https://github.com/rust-lang/rust/pull/132842 - https://github.com/rust-lang/rust/pull/132173 - https://github.com/rust-lang/rust/issues/131800 r? ``@workingjubilee``
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commit
2d9690d2e7
@ -36,9 +36,7 @@ fn do_check_abi<'tcx>(
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target_feature_def: DefId,
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target_feature_def: DefId,
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mut emit_err: impl FnMut(Option<&'static str>),
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mut emit_err: impl FnMut(Option<&'static str>),
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) {
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) {
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let Some(feature_def) = tcx.sess.target.features_for_correct_vector_abi() else {
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let feature_def = tcx.sess.target.features_for_correct_vector_abi();
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return;
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};
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let codegen_attrs = tcx.codegen_fn_attrs(target_feature_def);
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let codegen_attrs = tcx.codegen_fn_attrs(target_feature_def);
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for arg_abi in abi.args.iter().chain(std::iter::once(&abi.ret)) {
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for arg_abi in abi.args.iter().chain(std::iter::once(&abi.ret)) {
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let size = arg_abi.layout.size;
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let size = arg_abi.layout.size;
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@ -598,7 +598,12 @@ const S390X_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[
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const RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] =
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const RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] =
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&[/*(64, "zvl64b"), */ (128, "v")];
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&[/*(64, "zvl64b"), */ (128, "v")];
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// Always warn on SPARC, as the necessary target features cannot be enabled in Rust at the moment.
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// Always warn on SPARC, as the necessary target features cannot be enabled in Rust at the moment.
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const SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[/*(128, "vis")*/];
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const SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[/*(64, "vis")*/];
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const HEXAGON_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] =
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&[/*(512, "hvx-length64b"),*/ (1024, "hvx-length128b")];
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const MIPS_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "msa")];
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const CSKY_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "vdspv1")];
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impl super::spec::Target {
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impl super::spec::Target {
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pub fn rust_target_features(&self) -> &'static [(&'static str, Stability, ImpliedFeatures)] {
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pub fn rust_target_features(&self) -> &'static [(&'static str, Stability, ImpliedFeatures)] {
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@ -620,20 +625,24 @@ impl super::spec::Target {
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}
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}
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}
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}
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// Returns None if we do not support ABI checks on the given target yet.
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pub fn features_for_correct_vector_abi(&self) -> &'static [(u64, &'static str)] {
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pub fn features_for_correct_vector_abi(&self) -> Option<&'static [(u64, &'static str)]> {
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match &*self.arch {
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match &*self.arch {
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"x86" | "x86_64" => Some(X86_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"x86" | "x86_64" => X86_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"aarch64" | "arm64ec" => Some(AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"aarch64" | "arm64ec" => AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"arm" => Some(ARM_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"arm" => ARM_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"powerpc" | "powerpc64" => Some(POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"powerpc" | "powerpc64" => POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"loongarch64" => Some(&[]), // on-stack ABI, so we complain about all by-val vectors
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"loongarch64" => &[], // on-stack ABI, so we complain about all by-val vectors
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"riscv32" | "riscv64" => Some(RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"riscv32" | "riscv64" => RISCV_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"wasm32" | "wasm64" => Some(WASM_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"wasm32" | "wasm64" => WASM_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"s390x" => Some(S390X_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"s390x" => S390X_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"sparc" | "sparc64" => Some(SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI),
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"sparc" | "sparc64" => SPARC_FEATURES_FOR_CORRECT_VECTOR_ABI,
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// FIXME: add support for non-tier2 architectures
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"hexagon" => HEXAGON_FEATURES_FOR_CORRECT_VECTOR_ABI,
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_ => None,
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"mips" | "mips32r6" | "mips64" | "mips64r6" => MIPS_FEATURES_FOR_CORRECT_VECTOR_ABI,
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"bpf" => &[], // no vector ABI
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"csky" => CSKY_FEATURES_FOR_CORRECT_VECTOR_ABI,
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// FIXME: for some tier3 targets, we are overly cautious and always give warnings
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// when passing args in vector registers.
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_ => &[],
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}
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}
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}
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}
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