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Chore: add x86_amx_intrinsics
feature flag to core/lib.rs
and remove issue-120720-reduce-nan.rs
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@ -264,6 +264,7 @@
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#![feature(sse4a_target_feature)]
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#![feature(sse4a_target_feature)]
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#![feature(tbm_target_feature)]
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#![feature(tbm_target_feature)]
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#![feature(wasm_target_feature)]
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#![feature(wasm_target_feature)]
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#![feature(x86_amx_intrinsics)]
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// tidy-alphabetical-end
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// tidy-alphabetical-end
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// allow using `core::` in intra-doc links
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// allow using `core::` in intra-doc links
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@ -1,21 +0,0 @@
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//@ compile-flags: -C opt-level=3 -C target-cpu=cannonlake
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//@ only-x86_64
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// In a previous implementation, _mm512_reduce_add_pd did the reduction with all fast-math flags
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// enabled, making it UB to reduce a vector containing a NaN.
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#![crate_type = "lib"]
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#![feature(stdarch_x86_avx512, avx512_target_feature)]
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use std::arch::x86_64::*;
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// CHECK-LABEL: @demo(
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#[no_mangle]
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#[target_feature(enable = "avx512f")] // Function-level target feature mismatches inhibit inlining
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pub unsafe fn demo() -> bool {
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// CHECK: %0 = tail call reassoc double @llvm.vector.reduce.fadd.v8f64(
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// CHECK: %_0.i = fcmp uno double %0, 0.000000e+00
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// CHECK: ret i1 %_0.i
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let res =
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unsafe { _mm512_reduce_add_pd(_mm512_set_pd(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, f64::NAN)) };
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res.is_nan()
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}
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