Update the minimum external LLVM to 19

2025-04-14 04:56:49 +00:00 · 2025-04-02 12:08:01 -07:00 · 2025-04-02 12:08:01 -07:00 · 12167d7064
commit 12167d7064
parent 0c478fdfe1
70 changed files with 222 additions and 1911 deletions
--- a/compiler/rustc_codegen_llvm/src/abi.rs
+++ b/compiler/rustc_codegen_llvm/src/abi.rs
@ -17,14 +17,13 @@ use rustc_target::callconv::{
 use rustc_target::spec::SanitizerSet;
 use smallvec::SmallVec;

-use crate::attributes::llfn_attrs_from_instance;
+use crate::attributes::{self, llfn_attrs_from_instance};
 use crate::builder::Builder;
 use crate::context::CodegenCx;
 use crate::llvm::{self, Attribute, AttributePlace};
 use crate::type_::Type;
 use crate::type_of::LayoutLlvmExt;
 use crate::value::Value;
-use crate::{attributes, llvm_util};

 trait ArgAttributesExt {
    fn apply_attrs_to_llfn(&self, idx: AttributePlace, cx: &CodegenCx<'_, '_>, llfn: &Value);
@ -437,7 +436,6 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {

        let apply_range_attr = |idx: AttributePlace, scalar: rustc_abi::Scalar| {
            if cx.sess().opts.optimize != config::OptLevel::No
-                && llvm_util::get_version() >= (19, 0, 0)
                && matches!(scalar.primitive(), Primitive::Int(..))
                // If the value is a boolean, the range is 0..2 and that ultimately
                // become 0..0 when the type becomes i1, which would be rejected
@ -571,19 +569,6 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
            }
            _ => {}
        }
-        if bx.cx.sess().opts.optimize != config::OptLevel::No
-                && llvm_util::get_version() < (19, 0, 0)
-                && let BackendRepr::Scalar(scalar) = self.ret.layout.backend_repr
-                && matches!(scalar.primitive(), Primitive::Int(..))
-                // If the value is a boolean, the range is 0..2 and that ultimately
-                // become 0..0 when the type becomes i1, which would be rejected
-                // by the LLVM verifier.
-                && !scalar.is_bool()
-                // LLVM also rejects full range.
-                && !scalar.is_always_valid(bx)
-        {
-            bx.range_metadata(callsite, scalar.valid_range(bx));
-        }
        for arg in self.args.iter() {
            match &arg.mode {
                PassMode::Ignore => {}
--- a/compiler/rustc_codegen_llvm/src/attributes.rs
+++ b/compiler/rustc_codegen_llvm/src/attributes.rs
@ -407,30 +407,28 @@ pub(crate) fn llfn_attrs_from_instance<'ll, 'tcx>(
        // Do not set sanitizer attributes for naked functions.
        to_add.extend(sanitize_attrs(cx, codegen_fn_attrs.no_sanitize));

-        if llvm_util::get_version() >= (19, 0, 0) {
-            // For non-naked functions, set branch protection attributes on aarch64.
-            if let Some(BranchProtection { bti, pac_ret }) =
-                cx.sess().opts.unstable_opts.branch_protection
-            {
-                assert!(cx.sess().target.arch == "aarch64");
-                if bti {
-                    to_add.push(llvm::CreateAttrString(cx.llcx, "branch-target-enforcement"));
-                }
-                if let Some(PacRet { leaf, pc, key }) = pac_ret {
-                    if pc {
-                        to_add.push(llvm::CreateAttrString(cx.llcx, "branch-protection-pauth-lr"));
-                    }
-                    to_add.push(llvm::CreateAttrStringValue(
-                        cx.llcx,
-                        "sign-return-address",
-                        if leaf { "all" } else { "non-leaf" },
-                    ));
-                    to_add.push(llvm::CreateAttrStringValue(
-                        cx.llcx,
-                        "sign-return-address-key",
-                        if key == PAuthKey::A { "a_key" } else { "b_key" },
-                    ));
+        // For non-naked functions, set branch protection attributes on aarch64.
+        if let Some(BranchProtection { bti, pac_ret }) =
+            cx.sess().opts.unstable_opts.branch_protection
+        {
+            assert!(cx.sess().target.arch == "aarch64");
+            if bti {
+                to_add.push(llvm::CreateAttrString(cx.llcx, "branch-target-enforcement"));
+            }
+            if let Some(PacRet { leaf, pc, key }) = pac_ret {
+                if pc {
+                    to_add.push(llvm::CreateAttrString(cx.llcx, "branch-protection-pauth-lr"));
                }
+                to_add.push(llvm::CreateAttrStringValue(
+                    cx.llcx,
+                    "sign-return-address",
+                    if leaf { "all" } else { "non-leaf" },
+                ));
+                to_add.push(llvm::CreateAttrStringValue(
+                    cx.llcx,
+                    "sign-return-address-key",
+                    if key == PAuthKey::A { "a_key" } else { "b_key" },
+                ));
            }
        }
    }
@ -510,12 +508,6 @@ pub(crate) fn llfn_attrs_from_instance<'ll, 'tcx>(
            InstructionSetAttr::ArmA32 => "-thumb-mode".to_string(),
            InstructionSetAttr::ArmT32 => "+thumb-mode".to_string(),
        }))
-        // HACK: LLVM versions 19+ do not have the FPMR feature and treat it as always enabled
-        // It only exists as a feature in LLVM 18, cannot be passed down for any other version
-        .chain(match &*cx.tcx.sess.target.arch {
-            "aarch64" if llvm_util::get_version().0 == 18 => vec!["+fpmr".to_string()],
-            _ => vec![],
-        })
        .collect::<Vec<String>>();

    if cx.tcx.sess.target.is_like_wasm {
--- a/compiler/rustc_codegen_llvm/src/builder.rs
+++ b/compiler/rustc_codegen_llvm/src/builder.rs
@ -30,6 +30,7 @@ use smallvec::SmallVec;
 use tracing::{debug, instrument};

 use crate::abi::FnAbiLlvmExt;
+use crate::attributes;
 use crate::common::Funclet;
 use crate::context::{CodegenCx, FullCx, GenericCx, SCx};
 use crate::llvm::{
@ -38,7 +39,6 @@ use crate::llvm::{
 use crate::type_::Type;
 use crate::type_of::LayoutLlvmExt;
 use crate::value::Value;
-use crate::{attributes, llvm_util};

 #[must_use]
 pub(crate) struct GenericBuilder<'a, 'll, CX: Borrow<SCx<'ll>>> {
@ -927,11 +927,9 @@ impl<'a, 'll, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'll, 'tcx> {
        debug_assert_ne!(self.val_ty(val), dest_ty);

        let trunc = self.trunc(val, dest_ty);
-        if llvm_util::get_version() >= (19, 0, 0) {
-            unsafe {
-                if llvm::LLVMIsAInstruction(trunc).is_some() {
-                    llvm::LLVMSetNUW(trunc, True);
-                }
+        unsafe {
+            if llvm::LLVMIsAInstruction(trunc).is_some() {
+                llvm::LLVMSetNUW(trunc, True);
            }
        }
        trunc
@ -941,11 +939,9 @@ impl<'a, 'll, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'll, 'tcx> {
        debug_assert_ne!(self.val_ty(val), dest_ty);

        let trunc = self.trunc(val, dest_ty);
-        if llvm_util::get_version() >= (19, 0, 0) {
-            unsafe {
-                if llvm::LLVMIsAInstruction(trunc).is_some() {
-                    llvm::LLVMSetNSW(trunc, True);
-                }
+        unsafe {
+            if llvm::LLVMIsAInstruction(trunc).is_some() {
+                llvm::LLVMSetNSW(trunc, True);
            }
        }
        trunc
@ -1899,10 +1895,6 @@ impl<'a, 'll, 'tcx> Builder<'a, 'll, 'tcx> {
        hash: &'ll Value,
        bitmap_bits: &'ll Value,
    ) {
-        assert!(
-            crate::llvm_util::get_version() >= (19, 0, 0),
-            "MCDC intrinsics require LLVM 19 or later"
-        );
        self.call_intrinsic("llvm.instrprof.mcdc.parameters", &[fn_name, hash, bitmap_bits]);
    }

@ -1914,10 +1906,6 @@ impl<'a, 'll, 'tcx> Builder<'a, 'll, 'tcx> {
        bitmap_index: &'ll Value,
        mcdc_temp: &'ll Value,
    ) {
-        assert!(
-            crate::llvm_util::get_version() >= (19, 0, 0),
-            "MCDC intrinsics require LLVM 19 or later"
-        );
        let args = &[fn_name, hash, bitmap_index, mcdc_temp];
        self.call_intrinsic("llvm.instrprof.mcdc.tvbitmap.update", args);
    }
@ -1929,10 +1917,6 @@ impl<'a, 'll, 'tcx> Builder<'a, 'll, 'tcx> {

    #[instrument(level = "debug", skip(self))]
    pub(crate) fn mcdc_condbitmap_update(&mut self, cond_index: &'ll Value, mcdc_temp: &'ll Value) {
-        assert!(
-            crate::llvm_util::get_version() >= (19, 0, 0),
-            "MCDC intrinsics require LLVM 19 or later"
-        );
        let align = self.tcx.data_layout.i32_align.abi;
        let current_tv_index = self.load(self.cx.type_i32(), mcdc_temp, align);
        let new_tv_index = self.add(current_tv_index, cond_index);
--- a/compiler/rustc_codegen_llvm/src/context.rs
+++ b/compiler/rustc_codegen_llvm/src/context.rs
@ -164,23 +164,6 @@ pub(crate) unsafe fn create_module<'ll>(
    let mut target_data_layout = sess.target.data_layout.to_string();
    let llvm_version = llvm_util::get_version();

-    if llvm_version < (19, 0, 0) {
-        if sess.target.arch == "aarch64" || sess.target.arch.starts_with("arm64") {
-            // LLVM 19 sets -Fn32 in its data layout string for 64-bit ARM
-            // Earlier LLVMs leave this default, so remove it.
-            // See https://github.com/llvm/llvm-project/pull/90702
-            target_data_layout = target_data_layout.replace("-Fn32", "");
-        }
-    }
-
-    if llvm_version < (19, 0, 0) {
-        if sess.target.arch == "loongarch64" {
-            // LLVM 19 updates the LoongArch64 data layout.
-            // See https://github.com/llvm/llvm-project/pull/93814
-            target_data_layout = target_data_layout.replace("-n32:64", "-n64");
-        }
-    }
-
    if llvm_version < (20, 0, 0) {
        if sess.target.arch == "aarch64" || sess.target.arch.starts_with("arm64") {
            // LLVM 20 defines three additional address spaces for alternate
@ -1218,10 +1201,8 @@ impl<'ll> CodegenCx<'ll, '_> {

        if self.sess().instrument_coverage() {
            ifn!("llvm.instrprof.increment", fn(ptr, t_i64, t_i32, t_i32) -> void);
-            if crate::llvm_util::get_version() >= (19, 0, 0) {
-                ifn!("llvm.instrprof.mcdc.parameters", fn(ptr, t_i64, t_i32) -> void);
-                ifn!("llvm.instrprof.mcdc.tvbitmap.update", fn(ptr, t_i64, t_i32, ptr) -> void);
-            }
+            ifn!("llvm.instrprof.mcdc.parameters", fn(ptr, t_i64, t_i32) -> void);
+            ifn!("llvm.instrprof.mcdc.tvbitmap.update", fn(ptr, t_i64, t_i32, ptr) -> void);
        }

        ifn!("llvm.type.test", fn(ptr, t_metadata) -> i1);
--- a/compiler/rustc_codegen_llvm/src/llvm_util.rs
+++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs
@ -256,7 +256,6 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
        ("aarch64", "pmuv3") => Some(LLVMFeature::new("perfmon")),
        ("aarch64", "paca") => Some(LLVMFeature::new("pauth")),
        ("aarch64", "pacg") => Some(LLVMFeature::new("pauth")),
-        ("aarch64", "pauth-lr") if get_version().0 < 19 => None,
        // Before LLVM 20 those two features were packaged together as b16b16
        ("aarch64", "sve-b16b16") if get_version().0 < 20 => Some(LLVMFeature::new("b16b16")),
        ("aarch64", "sme-b16b16") if get_version().0 < 20 => Some(LLVMFeature::new("b16b16")),
@ -270,20 +269,9 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
        ("aarch64", "fhm") => Some(LLVMFeature::new("fp16fml")),
        ("aarch64", "fp16") => Some(LLVMFeature::new("fullfp16")),
        // Filter out features that are not supported by the current LLVM version
-        ("aarch64", "fpmr") if get_version().0 != 18 => None,
+        ("aarch64", "fpmr") => None, // only existed in 18
        ("arm", "fp16") => Some(LLVMFeature::new("fullfp16")),
-        // In LLVM 18, `unaligned-scalar-mem` was merged with `unaligned-vector-mem` into a single
-        // feature called `fast-unaligned-access`. In LLVM 19, it was split back out.
-        ("riscv32" | "riscv64", "unaligned-scalar-mem" | "unaligned-vector-mem")
-            if get_version().0 == 18 =>
-        {
-            Some(LLVMFeature::new("fast-unaligned-access"))
-        }
        // Filter out features that are not supported by the current LLVM version
-        ("riscv32" | "riscv64", "zaamo") if get_version().0 < 19 => None,
-        ("riscv32" | "riscv64", "zabha") if get_version().0 < 19 => None,
-        ("riscv32" | "riscv64", "zalrsc") if get_version().0 < 19 => None,
-        ("riscv32" | "riscv64", "zama16b") if get_version().0 < 19 => None,
        ("riscv32" | "riscv64", "zacas") if get_version().0 < 20 => None,
        // Enable the evex512 target feature if an avx512 target feature is enabled.
        ("x86", s) if s.starts_with("avx512") => {
@ -295,10 +283,9 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
        ("sparc", "leoncasa") => Some(LLVMFeature::new("hasleoncasa")),
        // In LLVM 19, there is no `v8plus` feature and `v9` means "SPARC-V9 instruction available and SPARC-V8+ ABI used".
        // https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp#L27-L28
-        // Before LLVM 19, there is no `v8plus` feature and `v9` means "SPARC-V9 instruction available".
+        // Before LLVM 19, there was no `v8plus` feature and `v9` means "SPARC-V9 instruction available".
        // https://github.com/llvm/llvm-project/blob/llvmorg-18.1.0/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp#L26
        ("sparc", "v8plus") if get_version().0 == 19 => Some(LLVMFeature::new("v9")),
-        ("sparc", "v8plus") if get_version().0 < 19 => None,
        ("powerpc", "power8-crypto") => Some(LLVMFeature::new("crypto")),
        // These new `amx` variants and `movrs` were introduced in LLVM20
        ("x86", "amx-avx512" | "amx-fp8" | "amx-movrs" | "amx-tf32" | "amx-transpose")
--- a/compiler/rustc_llvm/llvm-wrapper/CoverageMappingWrapper.cpp
+++ b/compiler/rustc_llvm/llvm-wrapper/CoverageMappingWrapper.cpp
@ -47,7 +47,6 @@ struct LLVMRustMCDCBranchParameters {
  int16_t ConditionIDs[2];
 };

-#if LLVM_VERSION_GE(19, 0)
 static coverage::mcdc::BranchParameters
 fromRust(LLVMRustMCDCBranchParameters Params) {
  return coverage::mcdc::BranchParameters(
@ -59,7 +58,6 @@ fromRust(LLVMRustMCDCDecisionParameters Params) {
  return coverage::mcdc::DecisionParameters(Params.BitmapIdx,
                                            Params.NumConditions);
 }
-#endif

 // Must match the layout of
 // `rustc_codegen_llvm::coverageinfo::ffi::CoverageSpan`.
@ -203,7 +201,6 @@ extern "C" void LLVMRustCoverageWriteFunctionMappingsToBuffer(
        Region.Span.LineEnd, Region.Span.ColumnEnd));
  }

-#if LLVM_VERSION_GE(19, 0)
  // MC/DC branch regions:
  for (const auto &Region : ArrayRef(MCDCBranchRegions, NumMCDCBranchRegions)) {
    MappingRegions.push_back(coverage::CounterMappingRegion::makeBranchRegion(
@ -221,7 +218,6 @@ extern "C" void LLVMRustCoverageWriteFunctionMappingsToBuffer(
        Region.Span.LineStart, Region.Span.ColumnStart, Region.Span.LineEnd,
        Region.Span.ColumnEnd));
  }
-#endif

  // Write the converted expressions and mappings to a byte buffer.
  auto CoverageMappingWriter = coverage::CoverageMappingWriter(
--- a/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp
+++ b/compiler/rustc_llvm/llvm-wrapper/PassWrapper.cpp
@ -47,10 +47,7 @@
 #include <vector>

 // Conditional includes prevent clang-format from fully sorting the list,
-// so keep them separate.
-#if LLVM_VERSION_GE(19, 0)
-#include "llvm/Support/PGOOptions.h"
-#endif
+// so if any are needed, keep them separate down here.

 using namespace llvm;

@ -432,31 +429,15 @@ extern "C" LLVMTargetMachineRef LLVMRustCreateTargetMachine(
  }
  if (!strcmp("zlib", DebugInfoCompression) &&
      llvm::compression::zlib::isAvailable()) {
-#if LLVM_VERSION_GE(19, 0)
    Options.MCOptions.CompressDebugSections = DebugCompressionType::Zlib;
-#else
-    Options.CompressDebugSections = DebugCompressionType::Zlib;
-#endif
  } else if (!strcmp("zstd", DebugInfoCompression) &&
             llvm::compression::zstd::isAvailable()) {
-#if LLVM_VERSION_GE(19, 0)
    Options.MCOptions.CompressDebugSections = DebugCompressionType::Zstd;
-#else
-    Options.CompressDebugSections = DebugCompressionType::Zstd;
-#endif
  } else if (!strcmp("none", DebugInfoCompression)) {
-#if LLVM_VERSION_GE(19, 0)
    Options.MCOptions.CompressDebugSections = DebugCompressionType::None;
-#else
-    Options.CompressDebugSections = DebugCompressionType::None;
-#endif
  }

-#if LLVM_VERSION_GE(19, 0)
  Options.MCOptions.X86RelaxRelocations = RelaxELFRelocations;
-#else
-  Options.RelaxELFRelocations = RelaxELFRelocations;
-#endif
  Options.UseInitArray = UseInitArray;
  Options.EmulatedTLS = UseEmulatedTls;

@ -753,34 +734,23 @@ extern "C" LLVMRustResult LLVMRustOptimize(
  auto FS = vfs::getRealFileSystem();
  if (PGOGenPath) {
    assert(!PGOUsePath && !PGOSampleUsePath);
-    PGOOpt = PGOOptions(PGOGenPath, "", "", "", FS, PGOOptions::IRInstr,
-                        PGOOptions::NoCSAction,
-#if LLVM_VERSION_GE(19, 0)
-                        PGOOptions::ColdFuncOpt::Default,
-#endif
-                        DebugInfoForProfiling);
+    PGOOpt = PGOOptions(
+        PGOGenPath, "", "", "", FS, PGOOptions::IRInstr, PGOOptions::NoCSAction,
+        PGOOptions::ColdFuncOpt::Default, DebugInfoForProfiling);
  } else if (PGOUsePath) {
    assert(!PGOSampleUsePath);
-    PGOOpt = PGOOptions(PGOUsePath, "", "", "", FS, PGOOptions::IRUse,
-                        PGOOptions::NoCSAction,
-#if LLVM_VERSION_GE(19, 0)
-                        PGOOptions::ColdFuncOpt::Default,
-#endif
-                        DebugInfoForProfiling);
+    PGOOpt = PGOOptions(
+        PGOUsePath, "", "", "", FS, PGOOptions::IRUse, PGOOptions::NoCSAction,
+        PGOOptions::ColdFuncOpt::Default, DebugInfoForProfiling);
  } else if (PGOSampleUsePath) {
-    PGOOpt = PGOOptions(PGOSampleUsePath, "", "", "", FS, PGOOptions::SampleUse,
-                        PGOOptions::NoCSAction,
-#if LLVM_VERSION_GE(19, 0)
-                        PGOOptions::ColdFuncOpt::Default,
-#endif
-                        DebugInfoForProfiling);
+    PGOOpt =
+        PGOOptions(PGOSampleUsePath, "", "", "", FS, PGOOptions::SampleUse,
+                   PGOOptions::NoCSAction, PGOOptions::ColdFuncOpt::Default,
+                   DebugInfoForProfiling);
  } else if (DebugInfoForProfiling) {
-    PGOOpt = PGOOptions("", "", "", "", FS, PGOOptions::NoAction,
-                        PGOOptions::NoCSAction,
-#if LLVM_VERSION_GE(19, 0)
-                        PGOOptions::ColdFuncOpt::Default,
-#endif
-                        DebugInfoForProfiling);
+    PGOOpt = PGOOptions(
+        "", "", "", "", FS, PGOOptions::NoAction, PGOOptions::NoCSAction,
+        PGOOptions::ColdFuncOpt::Default, DebugInfoForProfiling);
  }

  auto PB = PassBuilder(TM, PTO, PGOOpt, &PIC);
--- a/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp
+++ b/compiler/rustc_llvm/llvm-wrapper/RustWrapper.cpp
@ -473,12 +473,8 @@ extern "C" LLVMAttributeRef
 LLVMRustCreateRangeAttribute(LLVMContextRef C, unsigned NumBits,
                             const uint64_t LowerWords[],
                             const uint64_t UpperWords[]) {
-#if LLVM_VERSION_GE(19, 0)
  return LLVMCreateConstantRangeAttribute(C, Attribute::Range, NumBits,
                                          LowerWords, UpperWords);
-#else
-  report_fatal_error("LLVM 19.0 is required for Range Attribute");
-#endif
 }

 // These values **must** match ffi::AllocKindFlags.
@ -1601,43 +1597,6 @@ extern "C" LLVMValueRef LLVMRustBuildMemSet(LLVMBuilderRef B, LLVMValueRef Dst,
                                      MaybeAlign(DstAlign), IsVolatile));
 }

-// Polyfill for `LLVMBuildCallBr`, which was added in LLVM 19.
-// <https://github.com/llvm/llvm-project/commit/584253c4e2f788f870488fc32193b52d67ddaccc>
-// FIXME: Remove when Rust's minimum supported LLVM version reaches 19.
-#if LLVM_VERSION_LT(19, 0)
-DEFINE_SIMPLE_CONVERSION_FUNCTIONS(OperandBundleDef, LLVMOperandBundleRef)
-
-extern "C" LLVMValueRef
-LLVMBuildCallBr(LLVMBuilderRef B, LLVMTypeRef Ty, LLVMValueRef Fn,
-                LLVMBasicBlockRef DefaultDest, LLVMBasicBlockRef *IndirectDests,
-                unsigned NumIndirectDests, LLVMValueRef *Args, unsigned NumArgs,
-                LLVMOperandBundleRef *Bundles, unsigned NumBundles,
-                const char *Name) {
-  Value *Callee = unwrap(Fn);
-  FunctionType *FTy = unwrap<FunctionType>(Ty);
-
-  // FIXME: Is there a way around this?
-  std::vector<BasicBlock *> IndirectDestsUnwrapped;
-  IndirectDestsUnwrapped.reserve(NumIndirectDests);
-  for (unsigned i = 0; i < NumIndirectDests; ++i) {
-    IndirectDestsUnwrapped.push_back(unwrap(IndirectDests[i]));
-  }
-
-  // FIXME: Is there a way around this?
-  SmallVector<OperandBundleDef> OpBundles;
-  OpBundles.reserve(NumBundles);
-  for (unsigned i = 0; i < NumBundles; ++i) {
-    OpBundles.push_back(*unwrap(Bundles[i]));
-  }
-
-  return wrap(
-      unwrap(B)->CreateCallBr(FTy, Callee, unwrap(DefaultDest),
-                              ArrayRef<BasicBlock *>(IndirectDestsUnwrapped),
-                              ArrayRef<Value *>(unwrap(Args), NumArgs),
-                              ArrayRef<OperandBundleDef>(OpBundles), Name));
-}
-#endif
-
 extern "C" void LLVMRustPositionBuilderAtStart(LLVMBuilderRef B,
                                               LLVMBasicBlockRef BB) {
  auto Point = unwrap(BB)->getFirstInsertionPt();
@ -1781,24 +1740,6 @@ extern "C" LLVMValueRef LLVMRustBuildMaxNum(LLVMBuilderRef B, LLVMValueRef LHS,
  return wrap(unwrap(B)->CreateMaxNum(unwrap(LHS), unwrap(RHS)));
 }

-#if LLVM_VERSION_LT(19, 0)
-enum {
-  LLVMGEPFlagInBounds = (1 << 0),
-  LLVMGEPFlagNUSW = (1 << 1),
-  LLVMGEPFlagNUW = (1 << 2),
-};
-extern "C" LLVMValueRef
-LLVMBuildGEPWithNoWrapFlags(LLVMBuilderRef B, LLVMTypeRef Ty,
-                            LLVMValueRef Pointer, LLVMValueRef *Indices,
-                            unsigned NumIndices, const char *Name,
-                            unsigned NoWrapFlags) {
-  if (NoWrapFlags & LLVMGEPFlagInBounds)
-    return LLVMBuildInBoundsGEP2(B, Ty, Pointer, Indices, NumIndices, Name);
-  else
-    return LLVMBuildGEP2(B, Ty, Pointer, Indices, NumIndices, Name);
-}
-#endif
-
 // Transfers ownership of DiagnosticHandler unique_ptr to the caller.
 extern "C" DiagnosticHandler *
 LLVMRustContextGetDiagnosticHandler(LLVMContextRef C) {
@ -1866,11 +1807,7 @@ extern "C" void LLVMRustContextConfigureDiagnosticHandler(
        }
      }
      if (DiagnosticHandlerCallback) {
-#if LLVM_VERSION_GE(19, 0)
        DiagnosticHandlerCallback(&DI, DiagnosticHandlerContext);
-#else
-        DiagnosticHandlerCallback(DI, DiagnosticHandlerContext);
-#endif
        return true;
      }
      return false;
@ -2018,21 +1955,3 @@ extern "C" void LLVMRustSetNoSanitizeHWAddress(LLVMValueRef Global) {
  MD.NoHWAddress = true;
  GV.setSanitizerMetadata(MD);
 }
-
-// Operations on composite constants.
-// These are clones of LLVM api functions that will become available in future
-// releases. They can be removed once Rust's minimum supported LLVM version
-// supports them. See https://github.com/rust-lang/rust/issues/121868 See
-// https://llvm.org/doxygen/group__LLVMCCoreValueConstantComposite.html
-
-// FIXME: Remove when Rust's minimum supported LLVM version reaches 19.
-// https://github.com/llvm/llvm-project/commit/e1405e4f71c899420ebf8262d5e9745598419df8
-#if LLVM_VERSION_LT(19, 0)
-extern "C" LLVMValueRef LLVMConstStringInContext2(LLVMContextRef C,
-                                                  const char *Str,
-                                                  size_t Length,
-                                                  bool DontNullTerminate) {
-  return wrap(ConstantDataArray::getString(*unwrap(C), StringRef(Str, Length),
-                                           !DontNullTerminate));
-}
-#endif
--- a/src/bootstrap/src/core/build_steps/llvm.rs
+++ b/src/bootstrap/src/core/build_steps/llvm.rs
@ -346,8 +346,6 @@ impl Step for Llvm {
            .define("LLVM_INCLUDE_DOCS", "OFF")
            .define("LLVM_INCLUDE_BENCHMARKS", "OFF")
            .define("LLVM_INCLUDE_TESTS", enable_tests)
-            // FIXME: remove this when minimal llvm is 19
-            .define("LLVM_ENABLE_TERMINFO", "OFF")
            .define("LLVM_ENABLE_LIBEDIT", "OFF")
            .define("LLVM_ENABLE_BINDINGS", "OFF")
            .define("LLVM_ENABLE_Z3_SOLVER", "OFF")
@ -610,11 +608,11 @@ fn check_llvm_version(builder: &Builder<'_>, llvm_config: &Path) {
    let version = get_llvm_version(builder, llvm_config);
    let mut parts = version.split('.').take(2).filter_map(|s| s.parse::<u32>().ok());
    if let (Some(major), Some(_minor)) = (parts.next(), parts.next()) {
-        if major >= 18 {
+        if major >= 19 {
            return;
        }
    }
-    panic!("\n\nbad LLVM version: {version}, need >=18\n\n")
+    panic!("\n\nbad LLVM version: {version}, need >=19\n\n")
 }

 fn configure_cmake(
--- a/src/ci/docker/README.md
+++ b/src/ci/docker/README.md
@ -14,9 +14,9 @@ To run a specific CI job locally, you can use the `citool` Rust crate:
 cargo run --manifest-path src/ci/citool/Cargo.toml run-local <job-name>
 ```

-For example, to run the `x86_64-gnu-llvm-18-1` job:
+For example, to run the `x86_64-gnu-llvm-19-1` job:
 ```
-cargo run --manifest-path src/ci/citool/Cargo.toml run-local x86_64-gnu-llvm-18-1
+cargo run --manifest-path src/ci/citool/Cargo.toml run-local x86_64-gnu-llvm-19-1
 ```

 The job will output artifacts in an `obj/<image-name>` dir at the root of a repository. Note
@ -27,10 +27,10 @@ Docker image executed in the given CI job.
 while locally, to the `obj/<image-name>` directory. This is primarily to prevent
 strange linker errors when using multiple Docker images.

-For some Linux workflows (for example `x86_64-gnu-llvm-18-N`), the process is more involved. You will need to see which script is executed for the given workflow inside the [`jobs.yml`](../github-actions/jobs.yml) file and pass it through the `DOCKER_SCRIPT` environment variable. For example, to reproduce the `x86_64-gnu-llvm-18-3` workflow, you can run the following script:
+For some Linux workflows (for example `x86_64-gnu-llvm-19-N`), the process is more involved. You will need to see which script is executed for the given workflow inside the [`jobs.yml`](../github-actions/jobs.yml) file and pass it through the `DOCKER_SCRIPT` environment variable. For example, to reproduce the `x86_64-gnu-llvm-19-3` workflow, you can run the following script:

 ```
-DOCKER_SCRIPT=x86_64-gnu-llvm3.sh ./src/ci/docker/run.sh x86_64-gnu-llvm-18
+DOCKER_SCRIPT=x86_64-gnu-llvm3.sh ./src/ci/docker/run.sh x86_64-gnu-llvm-19
 ```

 ## Local Development
--- a/src/ci/docker/host-x86_64/x86_64-gnu-llvm-18/Dockerfile
+++ b/src/ci/docker/host-x86_64/x86_64-gnu-llvm-18/Dockerfile
@ -1,69 +0,0 @@
-FROM ubuntu:24.04
-
-ARG DEBIAN_FRONTEND=noninteractive
-
-RUN apt-get update && apt-get install -y --no-install-recommends \
-  bzip2 \
-  g++ \
-  gcc-multilib \
-  make \
-  ninja-build \
-  file \
-  curl \
-  ca-certificates \
-  python3 \
-  git \
-  cmake \
-  sudo \
-  gdb \
-  llvm-18-tools \
-  llvm-18-dev \
-  libedit-dev \
-  libssl-dev \
-  pkg-config \
-  zlib1g-dev \
-  xz-utils \
-  nodejs \
-  mingw-w64 \
-  # libgccjit dependencies
-  flex \
-  libmpfr-dev \
-  libgmp-dev \
-  libmpc3 \
-  libmpc-dev \
-  && rm -rf /var/lib/apt/lists/*
-
-# Install powershell (universal package) so we can test x.ps1 on Linux
-# FIXME: need a "universal" version that supports libicu74, but for now it still works to ignore that dep.
-RUN curl -sL "https://github.com/PowerShell/PowerShell/releases/download/v7.3.1/powershell_7.3.1-1.deb_amd64.deb" > powershell.deb && \
-    dpkg --ignore-depends=libicu72 -i powershell.deb && \
-    rm -f powershell.deb
-
-COPY scripts/sccache.sh /scripts/
-RUN sh /scripts/sccache.sh
-
-# We are disabling CI LLVM since this builder is intentionally using a host
-# LLVM, rather than the typical src/llvm-project LLVM.
-ENV NO_DOWNLOAD_CI_LLVM 1
-ENV EXTERNAL_LLVM 1
-
-# Using llvm-link-shared due to libffi issues -- see #34486
-ENV RUST_CONFIGURE_ARGS \
-      --build=x86_64-unknown-linux-gnu \
-      --llvm-root=/usr/lib/llvm-18 \
-      --enable-llvm-link-shared \
-      --set rust.randomize-layout=true \
-      --set rust.thin-lto-import-instr-limit=10
-
-COPY scripts/shared.sh /scripts/
-
-ARG SCRIPT_ARG
-
-COPY scripts/add_dummy_commit.sh /tmp/
-COPY scripts/x86_64-gnu-llvm.sh /tmp/
-COPY scripts/x86_64-gnu-llvm2.sh /tmp/
-COPY scripts/x86_64-gnu-llvm3.sh /tmp/
-COPY scripts/stage_2_test_set1.sh /tmp/
-COPY scripts/stage_2_test_set2.sh /tmp/
-
-ENV SCRIPT "/tmp/add_dummy_commit.sh && /tmp/${SCRIPT_ARG}"
--- a/src/ci/docker/host-x86_64/x86_64-gnu-llvm-19/Dockerfile
+++ b/src/ci/docker/host-x86_64/x86_64-gnu-llvm-19/Dockerfile
@ -3,6 +3,7 @@ FROM ubuntu:24.10
 ARG DEBIAN_FRONTEND=noninteractive

 RUN apt-get update && apt-get install -y --no-install-recommends \
+  bzip2 \
  g++ \
  gcc-multilib \
  make \
--- a/src/ci/github-actions/jobs.yml
+++ b/src/ci/github-actions/jobs.yml
@ -105,7 +105,7 @@ pr:
  - name: mingw-check-tidy
    continue_on_error: true
    <<: *job-linux-4c
-  - name: x86_64-gnu-llvm-18
+  - name: x86_64-gnu-llvm-19
    env:
      ENABLE_GCC_CODEGEN: "1"
      # We are adding (temporarily) a dummy commit on the compiler
@ -329,34 +329,6 @@ auto:
      DOCKER_SCRIPT: x86_64-gnu-llvm3.sh
    <<: *job-linux-4c

-  # The x86_64-gnu-llvm-18 job is split into multiple jobs to run tests in parallel.
-  # x86_64-gnu-llvm-18-1 skips tests that run in x86_64-gnu-llvm-18-{2,3}.
-  - name: x86_64-gnu-llvm-18-1
-    env:
-      RUST_BACKTRACE: 1
-      READ_ONLY_SRC: "0"
-      IMAGE: x86_64-gnu-llvm-18
-      DOCKER_SCRIPT: stage_2_test_set1.sh
-    <<: *job-linux-4c
-
-  # Skip tests that run in x86_64-gnu-llvm-18-{1,3}
-  - name: x86_64-gnu-llvm-18-2
-    env:
-      RUST_BACKTRACE: 1
-      READ_ONLY_SRC: "0"
-      IMAGE: x86_64-gnu-llvm-18
-      DOCKER_SCRIPT: x86_64-gnu-llvm2.sh
-    <<: *job-linux-4c
-
-  # Skip tests that run in x86_64-gnu-llvm-18-{1,2}
-  - name: x86_64-gnu-llvm-18-3
-    env:
-      RUST_BACKTRACE: 1
-      READ_ONLY_SRC: "0"
-      IMAGE: x86_64-gnu-llvm-18
-      DOCKER_SCRIPT: x86_64-gnu-llvm3.sh
-    <<: *job-linux-4c
-
  - name: x86_64-gnu-nopt
    <<: *job-linux-4c

--- a/tests/assembly/aarch64-pointer-auth.rs
+++ b/tests/assembly/aarch64-pointer-auth.rs
@ -8,7 +8,6 @@
 //@ [PACRET] compile-flags: -Z branch-protection=pac-ret,leaf
 //@ [PAUTHLR_NOP] compile-flags: -Z branch-protection=pac-ret,pc,leaf
 //@ [PAUTHLR] compile-flags: -C target-feature=+pauth-lr -Z branch-protection=pac-ret,pc,leaf
-//@ min-llvm-version: 19

 #![feature(no_core, lang_items)]
 #![no_std]
--- a/tests/assembly/static-relocation-model.rs
+++ b/tests/assembly/static-relocation-model.rs
@ -25,7 +25,7 @@ extern "C" {
 }

 // CHECK-LABEL: banana:
-// On the next line LLVM 14 produces a `movb`, whereas LLVM 15+ produces a `movzbl`.
+// LLVM may produce either kind of `mov` here, depending on version and optimization level.
 // x64: {{movb|movzbl}}   chaenomeles{{(\(%[a-z0-9]+\))?}}, %{{[a-z0-9]+}}
 // A64:      adrp    [[REG:[a-z0-9]+]], chaenomeles
 // A64-NEXT: ldrb    {{[a-z0-9]+}}, {{\[}}[[REG]], :lo12:chaenomeles]
--- a/tests/codegen/branch-protection-old-llvm.rs
+++ b/tests/codegen/branch-protection-old-llvm.rs
@ -1,46 +0,0 @@
-// Test that the correct module flags are emitted with different branch protection flags.
-
-//@ add-core-stubs
-//@ revisions: BTI PACRET LEAF BKEY NONE
-//@ needs-llvm-components: aarch64
-//@ [BTI] compile-flags: -Z branch-protection=bti
-//@ [PACRET] compile-flags: -Z branch-protection=pac-ret
-//@ [LEAF] compile-flags: -Z branch-protection=pac-ret,leaf
-//@ [BKEY] compile-flags: -Z branch-protection=pac-ret,b-key
-//@ compile-flags: --target aarch64-unknown-linux-gnu
-//@ max-llvm-major-version: 18
-
-#![crate_type = "lib"]
-#![feature(no_core, lang_items)]
-#![no_core]
-
-extern crate minicore;
-use minicore::*;
-
-// A basic test function.
-pub fn test() {}
-
-// BTI: !"branch-target-enforcement", i32 1
-// BTI: !"sign-return-address", i32 0
-// BTI: !"sign-return-address-all", i32 0
-// BTI: !"sign-return-address-with-bkey", i32 0
-
-// PACRET: !"branch-target-enforcement", i32 0
-// PACRET: !"sign-return-address", i32 1
-// PACRET: !"sign-return-address-all", i32 0
-// PACRET: !"sign-return-address-with-bkey", i32 0
-
-// LEAF: !"branch-target-enforcement", i32 0
-// LEAF: !"sign-return-address", i32 1
-// LEAF: !"sign-return-address-all", i32 1
-// LEAF: !"sign-return-address-with-bkey", i32 0
-
-// BKEY: !"branch-target-enforcement", i32 0
-// BKEY: !"sign-return-address", i32 1
-// BKEY: !"sign-return-address-all", i32 0
-// BKEY: !"sign-return-address-with-bkey", i32 1
-
-// NONE-NOT: branch-target-enforcement
-// NONE-NOT: sign-return-address
-// NONE-NOT: sign-return-address-all
-// NONE-NOT: sign-return-address-with-bkey
--- a/tests/codegen/branch-protection.rs
+++ b/tests/codegen/branch-protection.rs
@ -12,7 +12,6 @@
 //@ [PAUTHLR_LEAF] compile-flags: -Z branch-protection=pac-ret,pc,leaf
 //@ [PAUTHLR_BTI] compile-flags: -Z branch-protection=bti,pac-ret,pc
 //@ compile-flags: --target aarch64-unknown-linux-gnu
-//@ min-llvm-version: 19

 #![crate_type = "lib"]
 #![feature(no_core, lang_items)]
--- a/tests/codegen/call-metadata.rs
+++ b/tests/codegen/call-metadata.rs
@ -1,18 +0,0 @@
-// Checks that range metadata gets emitted on calls to functions returning a
-// scalar value.
-
-//@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
-//@ max-llvm-major-version: 18
-
-#![crate_type = "lib"]
-
-pub fn test() {
-    // CHECK: call noundef i8 @some_true(){{( #[0-9]+)?}}, !range [[R0:![0-9]+]]
-    // CHECK: [[R0]] = !{i8 0, i8 3}
-    some_true();
-}
-
-#[no_mangle]
-fn some_true() -> Option<bool> {
-    Some(true)
-}
--- a/tests/codegen/cast-target-abi.rs
+++ b/tests/codegen/cast-target-abi.rs
@ -1,7 +1,6 @@
 // ignore-tidy-linelength
 //@ add-core-stubs
 //@ revisions:aarch64 loongarch64 powerpc64 sparc64 x86_64
-//@ min-llvm-version: 19
 //@ compile-flags: -Copt-level=3 -Cno-prepopulate-passes -Zlint-llvm-ir

 //@[aarch64] compile-flags: --target aarch64-unknown-linux-gnu
--- a/tests/codegen/cffi/ffi-const.rs
+++ b/tests/codegen/cffi/ffi-const.rs
@ -9,8 +9,7 @@ pub fn bar() {
 extern "C" {
    // CHECK-LABEL: declare{{.*}}void @foo()
    // CHECK-SAME: [[ATTRS:#[0-9]+]]
-    // The attribute changed from `readnone` to `memory(none)` with LLVM 16.0.
-    // CHECK-DAG: attributes [[ATTRS]] = { {{.*}}{{readnone|memory\(none\)}}{{.*}} }
+    // CHECK-DAG: attributes [[ATTRS]] = { {{.*}}memory(none){{.*}} }
    #[ffi_const]
    pub fn foo();
 }
--- a/tests/codegen/cffi/ffi-out-of-bounds-loads.rs
+++ b/tests/codegen/cffi/ffi-out-of-bounds-loads.rs
@ -1,6 +1,5 @@
 //@ add-core-stubs
 //@ revisions: linux apple
-//@ min-llvm-version: 19
 //@ compile-flags: -Copt-level=0 -Cno-prepopulate-passes -Zlint-llvm-ir

 //@[linux] compile-flags: --target x86_64-unknown-linux-gnu
--- a/tests/codegen/cffi/ffi-pure.rs
+++ b/tests/codegen/cffi/ffi-pure.rs
@ -9,8 +9,7 @@ pub fn bar() {
 extern "C" {
    // CHECK-LABEL: declare{{.*}}void @foo()
    // CHECK-SAME: [[ATTRS:#[0-9]+]]
-    // The attribute changed from `readonly` to `memory(read)` with LLVM 16.0.
-    // CHECK-DAG: attributes [[ATTRS]] = { {{.*}}{{readonly|memory\(read\)}}{{.*}} }
+    // CHECK-DAG: attributes [[ATTRS]] = { {{.*}}memory(read){{.*}} }
    #[ffi_pure]
    pub fn foo();
 }
--- a/tests/codegen/debuginfo-proc-macro/mir_inlined_twice_var_locs.rs
+++ b/tests/codegen/debuginfo-proc-macro/mir_inlined_twice_var_locs.rs
@ -1,4 +1,3 @@
-//@ min-llvm-version: 19
 //@ compile-flags: -Cdebuginfo=2 -Copt-level=0 -Zmir-enable-passes=+Inline
 // MSVC is different because of the individual allocas.
 //@ ignore-msvc
--- a/tests/codegen/dont-shuffle-bswaps.rs
+++ b/tests/codegen/dont-shuffle-bswaps.rs
@ -3,7 +3,6 @@
 //@[OPT3] compile-flags: -C opt-level=3
 // some targets don't do the opt we are looking for
 //@[OPT3] only-64bit
-//@ min-llvm-version: 18.1.3

 #![crate_type = "lib"]
 #![no_std]
--- a/tests/codegen/enum/enum-two-variants-match.rs
+++ b/tests/codegen/enum/enum-two-variants-match.rs
@ -1,5 +1,4 @@
 //@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
-//@ min-llvm-version: 19 (for trunc nuw)
 //@ only-x86_64 (because these discriminants are isize)

 #![crate_type = "lib"]
--- a/tests/codegen/intrinsics/carrying_mul_add.rs
+++ b/tests/codegen/intrinsics/carrying_mul_add.rs
@ -1,7 +1,6 @@
 //@ revisions: RAW OPT
 //@ compile-flags: -C opt-level=1
 //@[RAW] compile-flags: -C no-prepopulate-passes
-//@[OPT] min-llvm-version: 19

 #![crate_type = "lib"]
 #![feature(core_intrinsics)]
--- a/tests/codegen/intrinsics/transmute.rs
+++ b/tests/codegen/intrinsics/transmute.rs
@ -12,9 +12,6 @@ use std::intrinsics::{transmute, transmute_unchecked};
 use std::mem::MaybeUninit;
 use std::num::NonZero;

-// FIXME(LLVM18REMOVED): `trunc nuw` doesn't exist in LLVM 18, so once we no
-// longer support it the optional flag checks can be changed to required.
-
 pub enum ZstNever {}

 #[repr(align(2))]
@ -157,7 +154,7 @@ pub unsafe fn check_from_newtype(x: Scalar64) -> u64 {
 pub unsafe fn check_aggregate_to_bool(x: Aggregate8) -> bool {
    // CHECK: %x = alloca [1 x i8], align 1
    // CHECK: %[[BYTE:.+]] = load i8, ptr %x, align 1
-    // CHECK: %[[BOOL:.+]] = trunc{{( nuw)?}} i8 %[[BYTE]] to i1
+    // CHECK: %[[BOOL:.+]] = trunc nuw i8 %[[BYTE]] to i1
    // CHECK: ret i1 %[[BOOL]]
    transmute(x)
 }
@ -175,7 +172,7 @@ pub unsafe fn check_aggregate_from_bool(x: bool) -> Aggregate8 {
 #[no_mangle]
 pub unsafe fn check_byte_to_bool(x: u8) -> bool {
    // CHECK-NOT: alloca
-    // CHECK: %[[R:.+]] = trunc{{( nuw)?}} i8 %x to i1
+    // CHECK: %[[R:.+]] = trunc nuw i8 %x to i1
    // CHECK: ret i1 %[[R]]
    transmute(x)
 }
@ -288,7 +285,7 @@ pub unsafe fn check_long_array_more_aligned(x: [u8; 100]) -> [u32; 25] {
 #[no_mangle]
 pub unsafe fn check_pair_with_bool(x: (u8, bool)) -> (bool, i8) {
    // CHECK-NOT: alloca
-    // CHECK: trunc{{( nuw)?}} i8 %x.0 to i1
+    // CHECK: trunc nuw i8 %x.0 to i1
    // CHECK: zext i1 %x.1 to i8
    transmute(x)
 }
@ -342,7 +339,7 @@ pub unsafe fn check_heterogeneous_integer_pair(x: (i32, bool)) -> (bool, u32) {
    // CHECK: store i8 %[[WIDER]]

    // CHECK: %[[BYTE:.+]] = load i8
-    // CHECK: trunc{{( nuw)?}} i8 %[[BYTE:.+]] to i1
+    // CHECK: trunc nuw i8 %[[BYTE:.+]] to i1
    // CHECK: load i32
    transmute(x)
 }
--- a/tests/codegen/issues/issue-107681-unwrap_unchecked.rs
+++ b/tests/codegen/issues/issue-107681-unwrap_unchecked.rs
@ -1,5 +1,4 @@
 //@ compile-flags: -Copt-level=3
-//@ min-llvm-version: 19

 // Test for #107681.
 // Make sure we don't create `br` or `select` instructions.
--- a/tests/codegen/issues/issue-118306.rs
+++ b/tests/codegen/issues/issue-118306.rs
@ -1,5 +1,4 @@
 //@ compile-flags: -Copt-level=3
-//@ min-llvm-version: 19
 //@ only-x86_64

 // Test for #118306.
--- a/tests/codegen/issues/issue-122600-ptr-discriminant-update.rs
+++ b/tests/codegen/issues/issue-122600-ptr-discriminant-update.rs
@ -1,5 +1,4 @@
 //@ compile-flags: -Copt-level=3
-//@ min-llvm-version: 19

 #![crate_type = "lib"]

--- a/tests/codegen/issues/issue-126585.rs
+++ b/tests/codegen/issues/issue-126585.rs
@ -1,5 +1,4 @@
 //@ compile-flags: -Copt-level=s
-//@ min-llvm-version: 19
 //@ only-x86_64

 // Test for #126585.
--- a/tests/codegen/range-attribute.rs
+++ b/tests/codegen/range-attribute.rs
@ -6,7 +6,6 @@
 //@[bit32] only-32bit
 //@[bit64] only-64bit
 //@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
-//@ min-llvm-version: 19

 #![crate_type = "lib"]

--- a/tests/codegen/tied-features-strength.rs
+++ b/tests/codegen/tied-features-strength.rs
@ -4,21 +4,17 @@
 //@ compile-flags: --crate-type=rlib --target=aarch64-unknown-linux-gnu
 //@ needs-llvm-components: aarch64

-// The "+fpmr" feature is matched as optional as it is only an explicit
-// feature in LLVM 18. Once the min supported version is LLVM-19 the optional
-// regex matching for this feature can be removed.
-
 //@ [ENABLE_SVE] compile-flags: -C target-feature=+sve -Copt-level=0
-// ENABLE_SVE: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+fpmr,?)?|(\+sve,?)|(\+neon,?)|(\+fp-armv8,?))*}}" }
+// ENABLE_SVE: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+sve,?)|(\+neon,?)|(\+fp-armv8,?))*}}" }

 //@ [DISABLE_SVE] compile-flags: -C target-feature=-sve -Copt-level=0
-// DISABLE_SVE: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+fpmr,?)?|(-sve,?)|(\+neon,?))*}}" }
+// DISABLE_SVE: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(-sve,?)|(\+neon,?))*}}" }

 //@ [DISABLE_NEON] compile-flags: -C target-feature=-neon -Copt-level=0
-// DISABLE_NEON: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+fpmr,?)?|(-fp-armv8,?)|(-neon,?))*}}" }
+// DISABLE_NEON: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(-fp-armv8,?)|(-neon,?))*}}" }

 //@ [ENABLE_NEON] compile-flags: -C target-feature=+neon -Copt-level=0
-// ENABLE_NEON: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+fpmr,?)?|(\+fp-armv8,?)|(\+neon,?))*}}" }
+// ENABLE_NEON: attributes #0 = { {{.*}} "target-features"="{{((\+outline-atomics,?)|(\+v8a,?)|(\+fp-armv8,?)|(\+neon,?))*}}" }

 #![feature(no_core, lang_items)]
 #![no_core]
--- a/tests/codegen/try_question_mark_nop.rs
+++ b/tests/codegen/try_question_mark_nop.rs
@ -1,10 +1,8 @@
 //@ compile-flags: -Copt-level=3 -Z merge-functions=disabled --edition=2021
 //@ only-x86_64
-// FIXME: Remove the `min-llvm-version`.
 //@ revisions: NINETEEN TWENTY
 //@[NINETEEN] exact-llvm-major-version: 19
 //@[TWENTY] min-llvm-version: 20
-//@ min-llvm-version: 19

 #![crate_type = "lib"]
 #![feature(try_blocks)]
--- a/tests/codegen/unchecked_shifts.rs
+++ b/tests/codegen/unchecked_shifts.rs
@ -1,7 +1,4 @@
-//@ revisions: LLVM18 LLVM19PLUS
 //@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
-//@[LLVM18] exact-llvm-major-version: 18
-//@[LLVM19PLUS] min-llvm-version: 19

 // This runs mir-opts to inline the standard library call, but doesn't run LLVM
 // optimizations so it doesn't need to worry about them adding more flags.
@ -24,8 +21,7 @@ pub unsafe fn unchecked_shl_unsigned_same(a: u32, b: u32) -> u32 {
 #[no_mangle]
 pub unsafe fn unchecked_shl_unsigned_smaller(a: u16, b: u32) -> u16 {
    // CHECK-NOT: assume
-    // LLVM18: %[[TRUNC:.+]] = trunc i32 %b to i16
-    // LLVM19PLUS: %[[TRUNC:.+]] = trunc nuw i32 %b to i16
+    // CHECK: %[[TRUNC:.+]] = trunc nuw i32 %b to i16
    // CHECK: shl i16 %a, %[[TRUNC]]
    a.unchecked_shl(b)
 }
@ -53,8 +49,7 @@ pub unsafe fn unchecked_shr_signed_same(a: i32, b: u32) -> i32 {
 #[no_mangle]
 pub unsafe fn unchecked_shr_signed_smaller(a: i16, b: u32) -> i16 {
    // CHECK-NOT: assume
-    // LLVM18: %[[TRUNC:.+]] = trunc i32 %b to i16
-    // LLVM19PLUS: %[[TRUNC:.+]] = trunc nuw i32 %b to i16
+    // CHECK: %[[TRUNC:.+]] = trunc nuw i32 %b to i16
    // CHECK: ashr i16 %a, %[[TRUNC]]
    a.unchecked_shr(b)
 }
@ -90,8 +85,7 @@ pub unsafe fn unchecked_shl_i128_u8(a: i128, b: u8) -> i128 {
 #[no_mangle]
 pub unsafe fn unchecked_shl_u8_i128(a: u8, b: i128) -> u8 {
    // CHECK-NOT: assume
-    // LLVM18: %[[TRUNC:.+]] = trunc i128 %b to i8
-    // LLVM19PLUS: %[[TRUNC:.+]] = trunc nuw i128 %b to i8
+    // CHECK: %[[TRUNC:.+]] = trunc nuw i128 %b to i8
    // CHECK: shl i8 %a, %[[TRUNC]]
    std::intrinsics::unchecked_shl(a, b)
 }
@ -100,8 +94,7 @@ pub unsafe fn unchecked_shl_u8_i128(a: u8, b: i128) -> u8 {
 #[no_mangle]
 pub unsafe fn unchecked_shr_i8_u128(a: i8, b: u128) -> i8 {
    // CHECK-NOT: assume
-    // LLVM18: %[[TRUNC:.+]] = trunc i128 %b to i8
-    // LLVM19PLUS: %[[TRUNC:.+]] = trunc nuw i128 %b to i8
+    // CHECK: %[[TRUNC:.+]] = trunc nuw i128 %b to i8
    // CHECK: ashr i8 %a, %[[TRUNC]]
    std::intrinsics::unchecked_shr(a, b)
 }
--- a/tests/codegen/vec_pop_push_noop.rs
+++ b/tests/codegen/vec_pop_push_noop.rs
@ -1,6 +1,3 @@
-//@ revisions: llvm-pre-19 llvm-19
-//@ [llvm-19] min-llvm-version: 19
-//@ [llvm-pre-19] max-llvm-major-version: 18
 //@ compile-flags: -Copt-level=3

 #![crate_type = "lib"]
--- a/tests/coverage/mcdc/condition-limit.cov-map
+++ b/tests/coverage/mcdc/condition-limit.cov-map
@ -1,5 +1,5 @@
 Function name: condition_limit::accept_7_conditions
-Raw bytes (147): 0x[01, 01, 08, 01, 05, 05, 09, 09, 0d, 0d, 11, 11, 15, 15, 19, 19, 1d, 01, 1d, 12, 01, 07, 01, 02, 09, 28, 08, 07, 02, 08, 00, 27, 30, 05, 02, 01, 07, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 07, 06, 00, 00, 0d, 00, 0e, 09, 00, 12, 00, 13, 30, 0d, 0a, 06, 05, 00, 00, 12, 00, 13, 0d, 00, 17, 00, 18, 30, 11, 0e, 05, 04, 00, 00, 17, 00, 18, 11, 00, 1c, 00, 1d, 30, 15, 12, 04, 03, 00, 00, 1c, 00, 1d, 15, 00, 21, 00, 22, 30, 19, 16, 03, 02, 00, 00, 21, 00, 22, 19, 00, 26, 00, 27, 30, 1d, 1a, 02, 00, 00, 00, 26, 00, 27, 1d, 00, 28, 02, 06, 1e, 02, 05, 00, 06, 01, 01, 01, 00, 02]
+Raw bytes (147): 0x[01, 01, 08, 01, 05, 05, 09, 09, 0d, 0d, 11, 11, 15, 15, 19, 19, 1d, 01, 1d, 12, 01, 06, 01, 02, 09, 28, 08, 07, 02, 08, 00, 27, 30, 05, 02, 01, 07, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 07, 06, 00, 00, 0d, 00, 0e, 09, 00, 12, 00, 13, 30, 0d, 0a, 06, 05, 00, 00, 12, 00, 13, 0d, 00, 17, 00, 18, 30, 11, 0e, 05, 04, 00, 00, 17, 00, 18, 11, 00, 1c, 00, 1d, 30, 15, 12, 04, 03, 00, 00, 1c, 00, 1d, 15, 00, 21, 00, 22, 30, 19, 16, 03, 02, 00, 00, 21, 00, 22, 19, 00, 26, 00, 27, 30, 1d, 1a, 02, 00, 00, 00, 26, 00, 27, 1d, 00, 28, 02, 06, 1e, 02, 05, 00, 06, 01, 01, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 8
@ -12,7 +12,7 @@ Number of expressions: 8
 - expression 6 operands: lhs = Counter(6), rhs = Counter(7)
 - expression 7 operands: lhs = Counter(0), rhs = Counter(7)
 Number of file 0 mappings: 18
- Code(Counter(0)) at (prev + 7, 1) to (start + 2, 9)
+- Code(Counter(0)) at (prev + 6, 1) to (start + 2, 9)
 - MCDCDecision { bitmap_idx: 8, conditions_num: 7 } at (prev + 2, 8) to (start + 0, 39)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 7, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
--- a/tests/coverage/mcdc/condition-limit.coverage
+++ b/tests/coverage/mcdc/condition-limit.coverage
@ -1,6 +1,5 @@
   LL|       |#![feature(coverage_attribute)]
   LL|       |//@ edition: 2021
-   LL|       |//@ min-llvm-version: 19
   LL|       |//@ compile-flags: -Zcoverage-options=mcdc
   LL|       |//@ llvm-cov-flags: --show-branches=count --show-mcdc
   LL|       |
--- a/tests/coverage/mcdc/condition-limit.rs
+++ b/tests/coverage/mcdc/condition-limit.rs
@ -1,6 +1,5 @@
 #![feature(coverage_attribute)]
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ compile-flags: -Zcoverage-options=mcdc
 //@ llvm-cov-flags: --show-branches=count --show-mcdc

--- a/tests/coverage/mcdc/if.cov-map
+++ b/tests/coverage/mcdc/if.cov-map
@ -1,5 +1,5 @@
 Function name: if::mcdc_check_a
-Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 0f, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 0e, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 3
@ -7,7 +7,7 @@ Number of expressions: 3
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 2 operands: lhs = Counter(0), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 15, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 14, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 14)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -23,7 +23,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: if::mcdc_check_b
-Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 17, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 16, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 3
@ -31,7 +31,7 @@ Number of expressions: 3
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 2 operands: lhs = Counter(0), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 23, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 22, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 14)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -47,7 +47,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: if::mcdc_check_both
-Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 1f, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 1e, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 3
@ -55,7 +55,7 @@ Number of expressions: 3
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 2 operands: lhs = Counter(0), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 31, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 30, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 14)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -71,7 +71,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: if::mcdc_check_neither
-Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 07, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (62): 0x[01, 01, 03, 01, 05, 05, 09, 01, 09, 08, 01, 06, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0d, 00, 0e, 30, 09, 06, 02, 00, 00, 00, 0d, 00, 0e, 09, 00, 0f, 02, 06, 0a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 3
@ -79,7 +79,7 @@ Number of expressions: 3
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 2 operands: lhs = Counter(0), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 7, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 6, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 14)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -95,7 +95,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: if::mcdc_check_not_tree_decision
-Raw bytes (85): 0x[01, 01, 07, 01, 05, 01, 17, 05, 09, 05, 09, 17, 0d, 05, 09, 01, 0d, 0a, 01, 31, 01, 03, 0a, 28, 05, 03, 03, 08, 00, 15, 30, 05, 02, 01, 02, 03, 00, 09, 00, 0a, 02, 00, 0e, 00, 0f, 30, 09, 06, 03, 02, 00, 00, 0e, 00, 0f, 17, 00, 14, 00, 15, 30, 0d, 12, 02, 00, 00, 00, 14, 00, 15, 0d, 00, 16, 02, 06, 1a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (85): 0x[01, 01, 07, 01, 05, 01, 17, 05, 09, 05, 09, 17, 0d, 05, 09, 01, 0d, 0a, 01, 30, 01, 03, 0a, 28, 05, 03, 03, 08, 00, 15, 30, 05, 02, 01, 02, 03, 00, 09, 00, 0a, 02, 00, 0e, 00, 0f, 30, 09, 06, 03, 02, 00, 00, 0e, 00, 0f, 17, 00, 14, 00, 15, 30, 0d, 12, 02, 00, 00, 00, 14, 00, 15, 0d, 00, 16, 02, 06, 1a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 7
@ -107,7 +107,7 @@ Number of expressions: 7
 - expression 5 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 6 operands: lhs = Counter(0), rhs = Counter(3)
 Number of file 0 mappings: 10
- Code(Counter(0)) at (prev + 49, 1) to (start + 3, 10)
+- Code(Counter(0)) at (prev + 48, 1) to (start + 3, 10)
 - MCDCDecision { bitmap_idx: 5, conditions_num: 3 } at (prev + 3, 8) to (start + 0, 21)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 3 } at (prev + 0, 9) to (start + 0, 10)
    true  = c1
@ -129,7 +129,7 @@ Number of file 0 mappings: 10
 Highest counter ID seen: c3

 Function name: if::mcdc_check_tree_decision
-Raw bytes (87): 0x[01, 01, 08, 01, 05, 05, 09, 05, 09, 05, 1f, 09, 0d, 09, 0d, 01, 1f, 09, 0d, 0a, 01, 27, 01, 03, 09, 28, 04, 03, 03, 08, 00, 15, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0e, 00, 0f, 30, 09, 0a, 02, 00, 03, 00, 0e, 00, 0f, 0a, 00, 13, 00, 14, 30, 0d, 0e, 03, 00, 00, 00, 13, 00, 14, 1f, 00, 16, 02, 06, 1a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (87): 0x[01, 01, 08, 01, 05, 05, 09, 05, 09, 05, 1f, 09, 0d, 09, 0d, 01, 1f, 09, 0d, 0a, 01, 26, 01, 03, 09, 28, 04, 03, 03, 08, 00, 15, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 05, 00, 0e, 00, 0f, 30, 09, 0a, 02, 00, 03, 00, 0e, 00, 0f, 0a, 00, 13, 00, 14, 30, 0d, 0e, 03, 00, 00, 00, 13, 00, 14, 1f, 00, 16, 02, 06, 1a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 8
@ -142,7 +142,7 @@ Number of expressions: 8
 - expression 6 operands: lhs = Counter(0), rhs = Expression(7, Add)
 - expression 7 operands: lhs = Counter(2), rhs = Counter(3)
 Number of file 0 mappings: 10
- Code(Counter(0)) at (prev + 39, 1) to (start + 3, 9)
+- Code(Counter(0)) at (prev + 38, 1) to (start + 3, 9)
 - MCDCDecision { bitmap_idx: 4, conditions_num: 3 } at (prev + 3, 8) to (start + 0, 21)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -164,7 +164,7 @@ Number of file 0 mappings: 10
 Highest counter ID seen: c3

 Function name: if::mcdc_nested_if
-Raw bytes (120): 0x[01, 01, 0b, 01, 05, 01, 2b, 05, 09, 05, 09, 2b, 0d, 05, 09, 0d, 11, 2b, 11, 05, 09, 01, 2b, 05, 09, 0e, 01, 3b, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 00, 02, 00, 08, 00, 09, 02, 00, 0d, 00, 0e, 30, 09, 26, 02, 00, 00, 00, 0d, 00, 0e, 2b, 01, 09, 01, 0d, 28, 06, 02, 01, 0c, 00, 12, 30, 0d, 12, 01, 02, 00, 00, 0c, 00, 0d, 0d, 00, 11, 00, 12, 30, 11, 1a, 02, 00, 00, 00, 11, 00, 12, 11, 00, 13, 02, 0a, 1e, 02, 09, 00, 0a, 26, 01, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (120): 0x[01, 01, 0b, 01, 05, 01, 2b, 05, 09, 05, 09, 2b, 0d, 05, 09, 0d, 11, 2b, 11, 05, 09, 01, 2b, 05, 09, 0e, 01, 3a, 01, 01, 09, 28, 03, 02, 01, 08, 00, 0e, 30, 05, 02, 01, 00, 02, 00, 08, 00, 09, 02, 00, 0d, 00, 0e, 30, 09, 26, 02, 00, 00, 00, 0d, 00, 0e, 2b, 01, 09, 01, 0d, 28, 06, 02, 01, 0c, 00, 12, 30, 0d, 12, 01, 02, 00, 00, 0c, 00, 0d, 0d, 00, 11, 00, 12, 30, 11, 1a, 02, 00, 00, 00, 11, 00, 12, 11, 00, 13, 02, 0a, 1e, 02, 09, 00, 0a, 26, 01, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 11
@ -180,7 +180,7 @@ Number of expressions: 11
 - expression 9 operands: lhs = Counter(0), rhs = Expression(10, Add)
 - expression 10 operands: lhs = Counter(1), rhs = Counter(2)
 Number of file 0 mappings: 14
- Code(Counter(0)) at (prev + 59, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 58, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 14)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 0, false_next_id: 2 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
--- a/tests/coverage/mcdc/if.coverage
+++ b/tests/coverage/mcdc/if.coverage
@ -1,6 +1,5 @@
   LL|       |#![feature(coverage_attribute)]
   LL|       |//@ edition: 2021
-   LL|       |//@ min-llvm-version: 19
   LL|       |//@ compile-flags: -Zcoverage-options=mcdc
   LL|       |//@ llvm-cov-flags: --show-branches=count --show-mcdc
   LL|       |
--- a/tests/coverage/mcdc/if.rs
+++ b/tests/coverage/mcdc/if.rs
@ -1,6 +1,5 @@
 #![feature(coverage_attribute)]
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ compile-flags: -Zcoverage-options=mcdc
 //@ llvm-cov-flags: --show-branches=count --show-mcdc

--- a/tests/coverage/mcdc/inlined_expressions.cov-map
+++ b/tests/coverage/mcdc/inlined_expressions.cov-map
@ -1,12 +1,12 @@
 Function name: inlined_expressions::inlined_instance
-Raw bytes (50): 0x[01, 01, 02, 01, 05, 05, 09, 06, 01, 08, 01, 01, 06, 28, 03, 02, 01, 05, 00, 0b, 30, 05, 02, 01, 02, 00, 00, 05, 00, 06, 05, 00, 0a, 00, 0b, 30, 09, 06, 02, 00, 00, 00, 0a, 00, 0b, 01, 01, 01, 00, 02]
+Raw bytes (50): 0x[01, 01, 02, 01, 05, 05, 09, 06, 01, 07, 01, 01, 06, 28, 03, 02, 01, 05, 00, 0b, 30, 05, 02, 01, 02, 00, 00, 05, 00, 06, 05, 00, 0a, 00, 0b, 30, 09, 06, 02, 00, 00, 00, 0a, 00, 0b, 01, 01, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 2
 - expression 0 operands: lhs = Counter(0), rhs = Counter(1)
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 Number of file 0 mappings: 6
- Code(Counter(0)) at (prev + 8, 1) to (start + 1, 6)
+- Code(Counter(0)) at (prev + 7, 1) to (start + 1, 6)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 1, 5) to (start + 0, 11)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 5) to (start + 0, 6)
    true  = c1
--- a/tests/coverage/mcdc/inlined_expressions.coverage
+++ b/tests/coverage/mcdc/inlined_expressions.coverage
@ -1,6 +1,5 @@
   LL|       |#![feature(coverage_attribute)]
   LL|       |//@ edition: 2021
-   LL|       |//@ min-llvm-version: 19
   LL|       |//@ compile-flags: -Zcoverage-options=mcdc -Copt-level=z -Cllvm-args=--inline-threshold=0
   LL|       |//@ llvm-cov-flags: --show-branches=count --show-mcdc
   LL|       |
--- a/tests/coverage/mcdc/inlined_expressions.rs
+++ b/tests/coverage/mcdc/inlined_expressions.rs
@ -1,6 +1,5 @@
 #![feature(coverage_attribute)]
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ compile-flags: -Zcoverage-options=mcdc -Copt-level=z -Cllvm-args=--inline-threshold=0
 //@ llvm-cov-flags: --show-branches=count --show-mcdc

--- a/tests/coverage/mcdc/nested_if.cov-map
+++ b/tests/coverage/mcdc/nested_if.cov-map
@ -1,5 +1,5 @@
 Function name: nested_if::doubly_nested_if_in_condition
-Raw bytes (170): 0x[01, 01, 0f, 01, 05, 05, 11, 05, 09, 05, 37, 09, 0d, 05, 09, 05, 1f, 09, 15, 15, 19, 05, 2b, 09, 19, 09, 0d, 05, 37, 09, 0d, 01, 11, 14, 01, 0f, 01, 01, 09, 28, 09, 02, 01, 08, 00, 4e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 11, 06, 02, 00, 00, 00, 0d, 00, 4e, 05, 00, 10, 00, 11, 28, 06, 02, 00, 10, 00, 36, 30, 09, 16, 01, 00, 02, 00, 10, 00, 11, 30, 0d, 32, 02, 00, 00, 00, 15, 00, 36, 16, 00, 18, 00, 19, 28, 03, 02, 00, 18, 00, 1e, 30, 15, 1a, 01, 02, 00, 00, 18, 00, 19, 15, 00, 1d, 00, 1e, 30, 19, 22, 02, 00, 00, 00, 1d, 00, 1e, 19, 00, 21, 00, 25, 26, 00, 2f, 00, 34, 37, 00, 39, 00, 3e, 32, 00, 48, 00, 4c, 11, 00, 4f, 02, 06, 3a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (170): 0x[01, 01, 0f, 01, 05, 05, 11, 05, 09, 05, 37, 09, 0d, 05, 09, 05, 1f, 09, 15, 15, 19, 05, 2b, 09, 19, 09, 0d, 05, 37, 09, 0d, 01, 11, 14, 01, 0e, 01, 01, 09, 28, 09, 02, 01, 08, 00, 4e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 11, 06, 02, 00, 00, 00, 0d, 00, 4e, 05, 00, 10, 00, 11, 28, 06, 02, 00, 10, 00, 36, 30, 09, 16, 01, 00, 02, 00, 10, 00, 11, 30, 0d, 32, 02, 00, 00, 00, 15, 00, 36, 16, 00, 18, 00, 19, 28, 03, 02, 00, 18, 00, 1e, 30, 15, 1a, 01, 02, 00, 00, 18, 00, 19, 15, 00, 1d, 00, 1e, 30, 19, 22, 02, 00, 00, 00, 1d, 00, 1e, 19, 00, 21, 00, 25, 26, 00, 2f, 00, 34, 37, 00, 39, 00, 3e, 32, 00, 48, 00, 4c, 11, 00, 4f, 02, 06, 3a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 15
@ -19,7 +19,7 @@ Number of expressions: 15
 - expression 13 operands: lhs = Counter(2), rhs = Counter(3)
 - expression 14 operands: lhs = Counter(0), rhs = Counter(4)
 Number of file 0 mappings: 20
- Code(Counter(0)) at (prev + 15, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 14, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 9, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 78)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -59,7 +59,7 @@ Number of file 0 mappings: 20
 Highest counter ID seen: c6

 Function name: nested_if::nested_if_in_condition
-Raw bytes (118): 0x[01, 01, 0a, 01, 05, 05, 11, 05, 09, 05, 09, 05, 23, 09, 0d, 09, 0d, 05, 23, 09, 0d, 01, 11, 0e, 01, 07, 01, 01, 09, 28, 06, 02, 01, 08, 00, 2e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 11, 06, 02, 00, 00, 00, 0d, 00, 2e, 05, 00, 10, 00, 11, 28, 03, 02, 00, 10, 00, 16, 30, 09, 0e, 01, 00, 02, 00, 10, 00, 11, 0e, 00, 15, 00, 16, 30, 0d, 1e, 02, 00, 00, 00, 15, 00, 16, 23, 00, 19, 00, 1d, 1e, 00, 27, 00, 2c, 11, 00, 2f, 02, 06, 26, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (118): 0x[01, 01, 0a, 01, 05, 05, 11, 05, 09, 05, 09, 05, 23, 09, 0d, 09, 0d, 05, 23, 09, 0d, 01, 11, 0e, 01, 06, 01, 01, 09, 28, 06, 02, 01, 08, 00, 2e, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 11, 06, 02, 00, 00, 00, 0d, 00, 2e, 05, 00, 10, 00, 11, 28, 03, 02, 00, 10, 00, 16, 30, 09, 0e, 01, 00, 02, 00, 10, 00, 11, 0e, 00, 15, 00, 16, 30, 0d, 1e, 02, 00, 00, 00, 15, 00, 16, 23, 00, 19, 00, 1d, 1e, 00, 27, 00, 2c, 11, 00, 2f, 02, 06, 26, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 10
@ -74,7 +74,7 @@ Number of expressions: 10
 - expression 8 operands: lhs = Counter(2), rhs = Counter(3)
 - expression 9 operands: lhs = Counter(0), rhs = Counter(4)
 Number of file 0 mappings: 14
- Code(Counter(0)) at (prev + 7, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 6, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 6, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 46)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -103,7 +103,7 @@ Number of file 0 mappings: 14
 Highest counter ID seen: c4

 Function name: nested_if::nested_in_then_block_in_condition
-Raw bytes (170): 0x[01, 01, 0f, 01, 05, 05, 19, 05, 09, 05, 09, 05, 37, 09, 0d, 09, 0d, 37, 11, 09, 0d, 11, 15, 37, 15, 09, 0d, 05, 37, 09, 0d, 01, 19, 14, 01, 22, 01, 01, 09, 28, 09, 02, 01, 08, 00, 4b, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 19, 06, 02, 00, 00, 00, 0d, 00, 4b, 05, 00, 10, 00, 11, 28, 03, 02, 00, 10, 00, 16, 30, 09, 0e, 01, 00, 02, 00, 10, 00, 11, 0e, 00, 15, 00, 16, 30, 0d, 32, 02, 00, 00, 00, 15, 00, 16, 37, 00, 1c, 00, 1d, 28, 06, 02, 00, 1c, 00, 22, 30, 11, 1e, 01, 02, 00, 00, 1c, 00, 1d, 11, 00, 21, 00, 22, 30, 15, 26, 02, 00, 00, 00, 21, 00, 22, 15, 00, 25, 00, 29, 2a, 00, 33, 00, 38, 32, 00, 44, 00, 49, 19, 00, 4c, 02, 06, 3a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (170): 0x[01, 01, 0f, 01, 05, 05, 19, 05, 09, 05, 09, 05, 37, 09, 0d, 09, 0d, 37, 11, 09, 0d, 11, 15, 37, 15, 09, 0d, 05, 37, 09, 0d, 01, 19, 14, 01, 21, 01, 01, 09, 28, 09, 02, 01, 08, 00, 4b, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 19, 06, 02, 00, 00, 00, 0d, 00, 4b, 05, 00, 10, 00, 11, 28, 03, 02, 00, 10, 00, 16, 30, 09, 0e, 01, 00, 02, 00, 10, 00, 11, 0e, 00, 15, 00, 16, 30, 0d, 32, 02, 00, 00, 00, 15, 00, 16, 37, 00, 1c, 00, 1d, 28, 06, 02, 00, 1c, 00, 22, 30, 11, 1e, 01, 02, 00, 00, 1c, 00, 1d, 11, 00, 21, 00, 22, 30, 15, 26, 02, 00, 00, 00, 21, 00, 22, 15, 00, 25, 00, 29, 2a, 00, 33, 00, 38, 32, 00, 44, 00, 49, 19, 00, 4c, 02, 06, 3a, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 15
@ -123,7 +123,7 @@ Number of expressions: 15
 - expression 13 operands: lhs = Counter(2), rhs = Counter(3)
 - expression 14 operands: lhs = Counter(0), rhs = Counter(6)
 Number of file 0 mappings: 20
- Code(Counter(0)) at (prev + 34, 1) to (start + 1, 9)
+- Code(Counter(0)) at (prev + 33, 1) to (start + 1, 9)
 - MCDCDecision { bitmap_idx: 9, conditions_num: 2 } at (prev + 1, 8) to (start + 0, 75)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
@ -163,7 +163,7 @@ Number of file 0 mappings: 20
 Highest counter ID seen: c6

 Function name: nested_if::nested_single_condition_decision
-Raw bytes (83): 0x[01, 01, 05, 01, 05, 05, 0d, 05, 09, 05, 09, 01, 0d, 0b, 01, 17, 01, 04, 09, 28, 03, 02, 04, 08, 00, 29, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 0d, 06, 02, 00, 00, 00, 0d, 00, 29, 05, 00, 10, 00, 11, 20, 09, 0e, 00, 10, 00, 11, 09, 00, 14, 00, 19, 0e, 00, 23, 00, 27, 0d, 00, 2a, 02, 06, 12, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
+Raw bytes (83): 0x[01, 01, 05, 01, 05, 05, 0d, 05, 09, 05, 09, 01, 0d, 0b, 01, 16, 01, 04, 09, 28, 03, 02, 04, 08, 00, 29, 30, 05, 02, 01, 02, 00, 00, 08, 00, 09, 30, 0d, 06, 02, 00, 00, 00, 0d, 00, 29, 05, 00, 10, 00, 11, 20, 09, 0e, 00, 10, 00, 11, 09, 00, 14, 00, 19, 0e, 00, 23, 00, 27, 0d, 00, 2a, 02, 06, 12, 02, 0c, 02, 06, 01, 03, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 5
@ -173,7 +173,7 @@ Number of expressions: 5
 - expression 3 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 4 operands: lhs = Counter(0), rhs = Counter(3)
 Number of file 0 mappings: 11
- Code(Counter(0)) at (prev + 23, 1) to (start + 4, 9)
+- Code(Counter(0)) at (prev + 22, 1) to (start + 4, 9)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 4, 8) to (start + 0, 41)
 - MCDCBranch { true: Counter(1), false: Expression(0, Sub), condition_id: 1, true_next_id: 2, false_next_id: 0 } at (prev + 0, 8) to (start + 0, 9)
    true  = c1
--- a/tests/coverage/mcdc/nested_if.coverage
+++ b/tests/coverage/mcdc/nested_if.coverage
@ -1,6 +1,5 @@
   LL|       |#![feature(coverage_attribute)]
   LL|       |//@ edition: 2021
-   LL|       |//@ min-llvm-version: 19
   LL|       |//@ compile-flags: -Zcoverage-options=mcdc
   LL|       |//@ llvm-cov-flags: --show-branches=count --show-mcdc
   LL|       |
--- a/tests/coverage/mcdc/nested_if.rs
+++ b/tests/coverage/mcdc/nested_if.rs
@ -1,6 +1,5 @@
 #![feature(coverage_attribute)]
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ compile-flags: -Zcoverage-options=mcdc
 //@ llvm-cov-flags: --show-branches=count --show-mcdc

--- a/tests/coverage/mcdc/non_control_flow.cov-map
+++ b/tests/coverage/mcdc/non_control_flow.cov-map
@ -1,5 +1,5 @@
 Function name: non_control_flow::assign_3
-Raw bytes (79): 0x[01, 01, 04, 01, 05, 01, 0b, 05, 09, 09, 0d, 0a, 01, 16, 01, 00, 28, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 04, 03, 00, 0d, 00, 18, 30, 05, 02, 01, 00, 02, 00, 0d, 00, 0e, 02, 00, 12, 00, 13, 30, 09, 06, 02, 03, 00, 00, 12, 00, 13, 09, 00, 17, 00, 18, 30, 0d, 0e, 03, 00, 00, 00, 17, 00, 18, 01, 01, 05, 01, 02]
+Raw bytes (79): 0x[01, 01, 04, 01, 05, 01, 0b, 05, 09, 09, 0d, 0a, 01, 15, 01, 00, 28, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 04, 03, 00, 0d, 00, 18, 30, 05, 02, 01, 00, 02, 00, 0d, 00, 0e, 02, 00, 12, 00, 13, 30, 09, 06, 02, 03, 00, 00, 12, 00, 13, 09, 00, 17, 00, 18, 30, 0d, 0e, 03, 00, 00, 00, 17, 00, 18, 01, 01, 05, 01, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 4
@ -8,7 +8,7 @@ Number of expressions: 4
 - expression 2 operands: lhs = Counter(1), rhs = Counter(2)
 - expression 3 operands: lhs = Counter(2), rhs = Counter(3)
 Number of file 0 mappings: 10
- Code(Counter(0)) at (prev + 22, 1) to (start + 0, 40)
+- Code(Counter(0)) at (prev + 21, 1) to (start + 0, 40)
 - Code(Counter(0)) at (prev + 1, 9) to (start + 0, 10)
 - Code(Counter(0)) at (prev + 0, 13) to (start + 0, 14)
 - MCDCDecision { bitmap_idx: 4, conditions_num: 3 } at (prev + 0, 13) to (start + 0, 24)
@ -28,7 +28,7 @@ Number of file 0 mappings: 10
 Highest counter ID seen: c3

 Function name: non_control_flow::assign_3_bis
-Raw bytes (81): 0x[01, 01, 05, 01, 05, 05, 09, 01, 09, 01, 13, 09, 0d, 0a, 01, 1b, 01, 00, 2c, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 05, 03, 00, 0d, 00, 18, 30, 05, 02, 01, 03, 02, 00, 0d, 00, 0e, 05, 00, 12, 00, 13, 30, 09, 06, 03, 00, 02, 00, 12, 00, 13, 0a, 00, 17, 00, 18, 30, 0d, 0e, 02, 00, 00, 00, 17, 00, 18, 01, 01, 05, 01, 02]
+Raw bytes (81): 0x[01, 01, 05, 01, 05, 05, 09, 01, 09, 01, 13, 09, 0d, 0a, 01, 1a, 01, 00, 2c, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 05, 03, 00, 0d, 00, 18, 30, 05, 02, 01, 03, 02, 00, 0d, 00, 0e, 05, 00, 12, 00, 13, 30, 09, 06, 03, 00, 02, 00, 12, 00, 13, 0a, 00, 17, 00, 18, 30, 0d, 0e, 02, 00, 00, 00, 17, 00, 18, 01, 01, 05, 01, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 5
@ -38,7 +38,7 @@ Number of expressions: 5
 - expression 3 operands: lhs = Counter(0), rhs = Expression(4, Add)
 - expression 4 operands: lhs = Counter(2), rhs = Counter(3)
 Number of file 0 mappings: 10
- Code(Counter(0)) at (prev + 27, 1) to (start + 0, 44)
+- Code(Counter(0)) at (prev + 26, 1) to (start + 0, 44)
 - Code(Counter(0)) at (prev + 1, 9) to (start + 0, 10)
 - Code(Counter(0)) at (prev + 0, 13) to (start + 0, 14)
 - MCDCDecision { bitmap_idx: 5, conditions_num: 3 } at (prev + 0, 13) to (start + 0, 24)
@ -58,14 +58,14 @@ Number of file 0 mappings: 10
 Highest counter ID seen: c3

 Function name: non_control_flow::assign_and
-Raw bytes (60): 0x[01, 01, 02, 01, 05, 05, 09, 08, 01, 0c, 01, 00, 21, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 03, 02, 00, 0d, 00, 13, 30, 05, 02, 01, 02, 00, 00, 0d, 00, 0e, 05, 00, 12, 00, 13, 30, 09, 06, 02, 00, 00, 00, 12, 00, 13, 01, 01, 05, 01, 02]
+Raw bytes (60): 0x[01, 01, 02, 01, 05, 05, 09, 08, 01, 0b, 01, 00, 21, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 03, 02, 00, 0d, 00, 13, 30, 05, 02, 01, 02, 00, 00, 0d, 00, 0e, 05, 00, 12, 00, 13, 30, 09, 06, 02, 00, 00, 00, 12, 00, 13, 01, 01, 05, 01, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 2
 - expression 0 operands: lhs = Counter(0), rhs = Counter(1)
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 12, 1) to (start + 0, 33)
+- Code(Counter(0)) at (prev + 11, 1) to (start + 0, 33)
 - Code(Counter(0)) at (prev + 1, 9) to (start + 0, 10)
 - Code(Counter(0)) at (prev + 0, 13) to (start + 0, 14)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 0, 13) to (start + 0, 19)
@ -80,7 +80,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: non_control_flow::assign_or
-Raw bytes (62): 0x[01, 01, 03, 01, 05, 01, 0b, 05, 09, 08, 01, 11, 01, 00, 20, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 03, 02, 00, 0d, 00, 13, 30, 05, 02, 01, 00, 02, 00, 0d, 00, 0e, 02, 00, 12, 00, 13, 30, 09, 06, 02, 00, 00, 00, 12, 00, 13, 01, 01, 05, 01, 02]
+Raw bytes (62): 0x[01, 01, 03, 01, 05, 01, 0b, 05, 09, 08, 01, 10, 01, 00, 20, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 03, 02, 00, 0d, 00, 13, 30, 05, 02, 01, 00, 02, 00, 0d, 00, 0e, 02, 00, 12, 00, 13, 30, 09, 06, 02, 00, 00, 00, 12, 00, 13, 01, 01, 05, 01, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 3
@ -88,7 +88,7 @@ Number of expressions: 3
 - expression 1 operands: lhs = Counter(0), rhs = Expression(2, Add)
 - expression 2 operands: lhs = Counter(1), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 17, 1) to (start + 0, 32)
+- Code(Counter(0)) at (prev + 16, 1) to (start + 0, 32)
 - Code(Counter(0)) at (prev + 1, 9) to (start + 0, 10)
 - Code(Counter(0)) at (prev + 0, 13) to (start + 0, 14)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 0, 13) to (start + 0, 19)
@ -104,23 +104,23 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: non_control_flow::foo
-Raw bytes (9): 0x[01, 01, 00, 01, 01, 25, 01, 02, 02]
+Raw bytes (9): 0x[01, 01, 00, 01, 01, 24, 01, 02, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 0
 Number of file 0 mappings: 1
- Code(Counter(0)) at (prev + 37, 1) to (start + 2, 2)
+- Code(Counter(0)) at (prev + 36, 1) to (start + 2, 2)
 Highest counter ID seen: c0

 Function name: non_control_flow::func_call
-Raw bytes (60): 0x[01, 01, 02, 01, 05, 05, 09, 08, 01, 29, 01, 00, 20, 01, 01, 05, 00, 08, 01, 00, 09, 00, 0a, 28, 03, 02, 00, 09, 00, 0f, 30, 05, 02, 01, 02, 00, 00, 09, 00, 0a, 05, 00, 0e, 00, 0f, 30, 09, 06, 02, 00, 00, 00, 0e, 00, 0f, 01, 01, 01, 00, 02]
+Raw bytes (60): 0x[01, 01, 02, 01, 05, 05, 09, 08, 01, 28, 01, 00, 20, 01, 01, 05, 00, 08, 01, 00, 09, 00, 0a, 28, 03, 02, 00, 09, 00, 0f, 30, 05, 02, 01, 02, 00, 00, 09, 00, 0a, 05, 00, 0e, 00, 0f, 30, 09, 06, 02, 00, 00, 00, 0e, 00, 0f, 01, 01, 01, 00, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 2
 - expression 0 operands: lhs = Counter(0), rhs = Counter(1)
 - expression 1 operands: lhs = Counter(1), rhs = Counter(2)
 Number of file 0 mappings: 8
- Code(Counter(0)) at (prev + 41, 1) to (start + 0, 32)
+- Code(Counter(0)) at (prev + 40, 1) to (start + 0, 32)
 - Code(Counter(0)) at (prev + 1, 5) to (start + 0, 8)
 - Code(Counter(0)) at (prev + 0, 9) to (start + 0, 10)
 - MCDCDecision { bitmap_idx: 3, conditions_num: 2 } at (prev + 0, 9) to (start + 0, 15)
@ -135,7 +135,7 @@ Number of file 0 mappings: 8
 Highest counter ID seen: c2

 Function name: non_control_flow::right_comb_tree
-Raw bytes (111): 0x[01, 01, 05, 01, 05, 05, 09, 09, 0d, 0d, 11, 11, 15, 0e, 01, 20, 01, 00, 41, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 06, 05, 00, 0d, 00, 2a, 30, 05, 02, 01, 02, 00, 00, 0d, 00, 0e, 05, 00, 13, 00, 14, 30, 09, 06, 02, 03, 00, 00, 13, 00, 14, 09, 00, 19, 00, 1a, 30, 0d, 0a, 03, 04, 00, 00, 19, 00, 1a, 0d, 00, 1f, 00, 20, 30, 11, 0e, 04, 05, 00, 00, 1f, 00, 20, 11, 00, 24, 00, 27, 30, 15, 12, 05, 00, 00, 00, 24, 00, 27, 01, 01, 05, 01, 02]
+Raw bytes (111): 0x[01, 01, 05, 01, 05, 05, 09, 09, 0d, 0d, 11, 11, 15, 0e, 01, 1f, 01, 00, 41, 01, 01, 09, 00, 0a, 01, 00, 0d, 00, 0e, 28, 06, 05, 00, 0d, 00, 2a, 30, 05, 02, 01, 02, 00, 00, 0d, 00, 0e, 05, 00, 13, 00, 14, 30, 09, 06, 02, 03, 00, 00, 13, 00, 14, 09, 00, 19, 00, 1a, 30, 0d, 0a, 03, 04, 00, 00, 19, 00, 1a, 0d, 00, 1f, 00, 20, 30, 11, 0e, 04, 05, 00, 00, 1f, 00, 20, 11, 00, 24, 00, 27, 30, 15, 12, 05, 00, 00, 00, 24, 00, 27, 01, 01, 05, 01, 02]
 Number of files: 1
 - file 0 => global file 1
 Number of expressions: 5
@ -145,7 +145,7 @@ Number of expressions: 5
 - expression 3 operands: lhs = Counter(3), rhs = Counter(4)
 - expression 4 operands: lhs = Counter(4), rhs = Counter(5)
 Number of file 0 mappings: 14
- Code(Counter(0)) at (prev + 32, 1) to (start + 0, 65)
+- Code(Counter(0)) at (prev + 31, 1) to (start + 0, 65)
 - Code(Counter(0)) at (prev + 1, 9) to (start + 0, 10)
 - Code(Counter(0)) at (prev + 0, 13) to (start + 0, 14)
 - MCDCDecision { bitmap_idx: 6, conditions_num: 5 } at (prev + 0, 13) to (start + 0, 42)
--- a/tests/coverage/mcdc/non_control_flow.coverage
+++ b/tests/coverage/mcdc/non_control_flow.coverage
@ -1,6 +1,5 @@
   LL|       |#![feature(coverage_attribute)]
   LL|       |//@ edition: 2021
-   LL|       |//@ min-llvm-version: 19
   LL|       |//@ compile-flags: -Zcoverage-options=mcdc
   LL|       |//@ llvm-cov-flags: --show-branches=count --show-mcdc
   LL|       |
--- a/tests/coverage/mcdc/non_control_flow.rs
+++ b/tests/coverage/mcdc/non_control_flow.rs
@ -1,6 +1,5 @@
 #![feature(coverage_attribute)]
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ compile-flags: -Zcoverage-options=mcdc
 //@ llvm-cov-flags: --show-branches=count --show-mcdc

--- a/tests/ui/abi/large-byval-align.rs
+++ b/tests/ui/abi/large-byval-align.rs
@ -1,6 +1,5 @@
 //@ compile-flags: -Copt-level=0
 //@ only-x86_64
-//@ min-llvm-version: 19
 //@ build-pass

 #[repr(align(536870912))]
--- a/tests/ui/asm/aarch64/srcloc.old.stderr
+++ b/tests/ui/asm/aarch64/srcloc.old.stderr
@ -1,290 +0,0 @@
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:15:15
-   |
-LL |         asm!("invalid_instruction");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:19:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:13
-   |
-LL |             invalid_instruction
-   |             ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:24:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:13
-   |
-LL |             invalid_instruction
-   |             ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:30:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:13
-   |
-LL |             invalid_instruction
-   |             ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:37:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:13
-   |
-LL |             invalid_instruction
-   |             ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:42:14
-   |
-LL |         asm!(concat!("invalid", "_", "instruction"));
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:46:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:52:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:59:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:66:13
-   |
-LL |             concat!("invalid", "_", "instruction"),
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:73:13
-   |
-LL |             concat!("invalid", "_", "instruction"),
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:80:14
-   |
-LL |             "invalid_instruction1",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction1
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:81:14
-   |
-LL |             "invalid_instruction2",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction2
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:87:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction1
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:87:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction2
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:96:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction1
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:96:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction2
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:100:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction3
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:100:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:1
-   |
-LL | invalid_instruction4
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:111:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     invalid_instruction1
-   |     ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:111:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:1
-   |
-LL | invalid_instruction2
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:115:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:1
-   |
-LL | invalid_instruction3
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:115:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:5:1
-   |
-LL | invalid_instruction4
-   | ^
-
-error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:128:14
-   |
-LL |             "invalid_instruction"
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:1
-   |
-LL | invalid_instruction
-   | ^
-
-error: aborting due to 24 previous errors
-
--- a/tests/ui/asm/aarch64/srcloc.rs
+++ b/tests/ui/asm/aarch64/srcloc.rs
@ -1,10 +1,7 @@
-//@ revisions: old new
 //@ only-aarch64
 //@ build-fail
 //@ needs-asm-support
 //@ compile-flags: -Ccodegen-units=1
-//@[old] ignore-llvm-version: 19 - 99
-//@[new] min-llvm-version: 19

 use std::arch::asm;

--- a/tests/ui/asm/aarch64/srcloc.new.stderr
+++ b/tests/ui/asm/aarch64/srcloc.new.stderr
@ -1,5 +1,5 @@
 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:15:15
+  --> $DIR/srcloc.rs:12:15
   |
 LL |         asm!("invalid_instruction");
   |               ^^^^^^^^^^^^^^^^^^^
@ -11,7 +11,7 @@ LL |     invalid_instruction
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:19:13
+  --> $DIR/srcloc.rs:16:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -23,7 +23,7 @@ LL |             invalid_instruction
   |             ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:24:13
+  --> $DIR/srcloc.rs:21:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -35,7 +35,7 @@ LL |             invalid_instruction
   |             ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:30:13
+  --> $DIR/srcloc.rs:27:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -47,7 +47,7 @@ LL |             invalid_instruction
   |             ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:37:13
+  --> $DIR/srcloc.rs:34:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -59,7 +59,7 @@ LL |             invalid_instruction
   |             ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:42:14
+  --> $DIR/srcloc.rs:39:14
   |
 LL |         asm!(concat!("invalid", "_", "instruction"));
   |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -71,7 +71,7 @@ LL |     invalid_instruction
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:46:14
+  --> $DIR/srcloc.rs:43:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -83,7 +83,7 @@ LL |     invalid_instruction
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:52:14
+  --> $DIR/srcloc.rs:49:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -95,7 +95,7 @@ LL | invalid_instruction
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:59:14
+  --> $DIR/srcloc.rs:56:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -107,7 +107,7 @@ LL | invalid_instruction
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:66:13
+  --> $DIR/srcloc.rs:63:13
   |
 LL |             concat!("invalid", "_", "instruction"),
   |             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -119,7 +119,7 @@ LL | invalid_instruction
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:73:13
+  --> $DIR/srcloc.rs:70:13
   |
 LL |             concat!("invalid", "_", "instruction"),
   |             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -131,7 +131,7 @@ LL | invalid_instruction
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:80:14
+  --> $DIR/srcloc.rs:77:14
   |
 LL |             "invalid_instruction1",
   |              ^^^^^^^^^^^^^^^^^^^^
@ -143,7 +143,7 @@ LL |     invalid_instruction1
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:81:14
+  --> $DIR/srcloc.rs:78:14
   |
 LL |             "invalid_instruction2",
   |              ^^^^^^^^^^^^^^^^^^^^
@ -155,7 +155,7 @@ LL | invalid_instruction2
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:87:13
+  --> $DIR/srcloc.rs:84:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -170,7 +170,7 @@ LL |     invalid_instruction1
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:87:13
+  --> $DIR/srcloc.rs:84:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -185,7 +185,7 @@ LL | invalid_instruction2
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:96:13
+  --> $DIR/srcloc.rs:93:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -200,7 +200,7 @@ LL |     invalid_instruction1
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:96:13
+  --> $DIR/srcloc.rs:93:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -215,7 +215,7 @@ LL | invalid_instruction2
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:100:13
+  --> $DIR/srcloc.rs:97:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -230,7 +230,7 @@ LL | invalid_instruction3
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:100:13
+  --> $DIR/srcloc.rs:97:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -245,7 +245,7 @@ LL | invalid_instruction4
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:111:13
+  --> $DIR/srcloc.rs:108:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -260,7 +260,7 @@ LL |     invalid_instruction1
   |     ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:111:13
+  --> $DIR/srcloc.rs:108:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -275,7 +275,7 @@ LL | invalid_instruction2
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:115:13
+  --> $DIR/srcloc.rs:112:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -290,7 +290,7 @@ LL | invalid_instruction3
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:115:13
+  --> $DIR/srcloc.rs:112:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -305,7 +305,7 @@ LL | invalid_instruction4
   | ^

 error: unrecognized instruction mnemonic
-  --> $DIR/srcloc.rs:128:14
+  --> $DIR/srcloc.rs:125:14
   |
 LL |             "invalid_instruction"
   |              ^^^^^^^^^^^^^^^^^^^
--- a/tests/ui/asm/inline-syntax.arm.stderr
+++ b/tests/ui/asm/inline-syntax.arm.stderr
@ -15,7 +15,7 @@ LL | .intel_syntax noprefix
   | ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:26:15
+  --> $DIR/inline-syntax.rs:21:15
   |
 LL |         asm!(".intel_syntax noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^
@ -27,7 +27,7 @@ LL |     .intel_syntax noprefix
   |     ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:30:15
+  --> $DIR/inline-syntax.rs:24:15
   |
 LL |         asm!(".intel_syntax aaa noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -39,7 +39,7 @@ LL |     .intel_syntax aaa noprefix
   |     ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:34:15
+  --> $DIR/inline-syntax.rs:27:15
   |
 LL |         asm!(".att_syntax noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^
@ -51,7 +51,7 @@ LL |     .att_syntax noprefix
   |     ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:38:15
+  --> $DIR/inline-syntax.rs:30:15
   |
 LL |         asm!(".att_syntax bbb noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^^^
@ -63,7 +63,7 @@ LL |     .att_syntax bbb noprefix
   |     ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:42:15
+  --> $DIR/inline-syntax.rs:33:15
   |
 LL |         asm!(".intel_syntax noprefix; nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -75,7 +75,7 @@ LL |     .intel_syntax noprefix; nop
   |     ^

 error: unknown directive
-  --> $DIR/inline-syntax.rs:49:13
+  --> $DIR/inline-syntax.rs:39:13
   |
 LL |             .intel_syntax noprefix
   |             ^^^^^^^^^^^^^^^^^^^^^^
--- a/tests/ui/asm/inline-syntax.arm_llvm_18.stderr
+++ b/tests/ui/asm/inline-syntax.arm_llvm_18.stderr
@ -1,90 +0,0 @@
-error: unknown directive
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:1
-   |
-LL | .intel_syntax noprefix
-   | ^
-
-error: unknown directive
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:1
-   |
-LL | .intel_syntax noprefix
-   | ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:26:15
-   |
-LL |         asm!(".intel_syntax noprefix", "nop");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     .intel_syntax noprefix
-   |     ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:30:15
-   |
-LL |         asm!(".intel_syntax aaa noprefix", "nop");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     .intel_syntax aaa noprefix
-   |     ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:34:15
-   |
-LL |         asm!(".att_syntax noprefix", "nop");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     .att_syntax noprefix
-   |     ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:38:15
-   |
-LL |         asm!(".att_syntax bbb noprefix", "nop");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     .att_syntax bbb noprefix
-   |     ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:42:15
-   |
-LL |         asm!(".intel_syntax noprefix; nop");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:2
-   |
-LL |     .intel_syntax noprefix; nop
-   |     ^
-
-error: unknown directive
-  --> $DIR/inline-syntax.rs:49:13
-   |
-LL |             .intel_syntax noprefix
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:13
-   |
-LL |             .intel_syntax noprefix
-   |             ^
-
-error: aborting due to 8 previous errors
-
--- a/tests/ui/asm/inline-syntax.rs
+++ b/tests/ui/asm/inline-syntax.rs
@ -1,17 +1,12 @@
 //@ add-core-stubs
-//@ revisions: x86_64 arm_llvm_18 arm
+//@ revisions: x86_64 arm
 //@[x86_64] compile-flags: --target x86_64-unknown-linux-gnu
 //@[x86_64] check-pass
 //@[x86_64] needs-llvm-components: x86
-//@[arm_llvm_18] compile-flags: --target armv7-unknown-linux-gnueabihf
-//@[arm_llvm_18] build-fail
-//@[arm_llvm_18] needs-llvm-components: arm
-//@[arm_llvm_18] ignore-llvm-version: 19 - 99
 // LLVM 19+ has full support for 64-bit cookies.
 //@[arm] compile-flags: --target armv7-unknown-linux-gnueabihf
 //@[arm] build-fail
 //@[arm] needs-llvm-components: arm
-//@[arm] min-llvm-version: 19
 //@ needs-asm-support

 #![feature(no_core)]
@ -26,23 +21,18 @@ pub fn main() {
        asm!(".intel_syntax noprefix", "nop");
        //[x86_64]~^ WARN avoid using `.intel_syntax`
        //[arm]~^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^ ERROR unknown directive
        asm!(".intel_syntax aaa noprefix", "nop");
        //[x86_64]~^ WARN avoid using `.intel_syntax`
        //[arm]~^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^ ERROR unknown directive
        asm!(".att_syntax noprefix", "nop");
        //[x86_64]~^ WARN avoid using `.att_syntax`
        //[arm]~^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^ ERROR unknown directive
        asm!(".att_syntax bbb noprefix", "nop");
        //[x86_64]~^ WARN avoid using `.att_syntax`
        //[arm]~^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^ ERROR unknown directive
        asm!(".intel_syntax noprefix; nop");
        //[x86_64]~^ WARN avoid using `.intel_syntax`
        //[arm]~^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^ ERROR unknown directive

        asm!(
            r"
@ -51,7 +41,6 @@ pub fn main() {
        );
        //[x86_64]~^^^ WARN avoid using `.intel_syntax`
        //[arm]~^^^^ ERROR unknown directive
-        //[arm_llvm_18]~^^^^^ ERROR unknown directive
    }
 }

@ -59,7 +48,5 @@ global_asm!(".intel_syntax noprefix", "nop");
 //[x86_64]~^ WARN avoid using `.intel_syntax`
 // Global assembly errors don't have line numbers, so no error on ARM.

-//[arm_llvm_18]~? ERROR unknown directive
-//[arm_llvm_18]~? ERROR unknown directive
 //[arm]~? ERROR unknown directive
 //[arm]~? ERROR unknown directive
--- a/tests/ui/asm/inline-syntax.x86_64.stderr
+++ b/tests/ui/asm/inline-syntax.x86_64.stderr
@ -1,5 +1,5 @@
 warning: avoid using `.intel_syntax`, Intel syntax is the default
-  --> $DIR/inline-syntax.rs:58:14
+  --> $DIR/inline-syntax.rs:47:14
   |
 LL | global_asm!(".intel_syntax noprefix", "nop");
   |              ^^^^^^^^^^^^^^^^^^^^^^
@ -7,37 +7,37 @@ LL | global_asm!(".intel_syntax noprefix", "nop");
   = note: `#[warn(bad_asm_style)]` on by default

 warning: avoid using `.intel_syntax`, Intel syntax is the default
-  --> $DIR/inline-syntax.rs:26:15
+  --> $DIR/inline-syntax.rs:21:15
   |
 LL |         asm!(".intel_syntax noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^

 warning: avoid using `.intel_syntax`, Intel syntax is the default
-  --> $DIR/inline-syntax.rs:30:15
+  --> $DIR/inline-syntax.rs:24:15
   |
 LL |         asm!(".intel_syntax aaa noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^^^^^

 warning: avoid using `.att_syntax`, prefer using `options(att_syntax)` instead
-  --> $DIR/inline-syntax.rs:34:15
+  --> $DIR/inline-syntax.rs:27:15
   |
 LL |         asm!(".att_syntax noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^

 warning: avoid using `.att_syntax`, prefer using `options(att_syntax)` instead
-  --> $DIR/inline-syntax.rs:38:15
+  --> $DIR/inline-syntax.rs:30:15
   |
 LL |         asm!(".att_syntax bbb noprefix", "nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^^^

 warning: avoid using `.intel_syntax`, Intel syntax is the default
-  --> $DIR/inline-syntax.rs:42:15
+  --> $DIR/inline-syntax.rs:33:15
   |
 LL |         asm!(".intel_syntax noprefix; nop");
   |               ^^^^^^^^^^^^^^^^^^^^^^

 warning: avoid using `.intel_syntax`, Intel syntax is the default
-  --> $DIR/inline-syntax.rs:49:13
+  --> $DIR/inline-syntax.rs:39:13
   |
 LL |             .intel_syntax noprefix
   |             ^^^^^^^^^^^^^^^^^^^^^^
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr
@ -1,5 +1,5 @@
 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
+  --> $DIR/riscv32e-registers.rs:42:11
   |
 LL |     asm!("li x16, 0");
   |           ^^^^^^^^^
@ -11,7 +11,7 @@ LL |     li x16, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
+  --> $DIR/riscv32e-registers.rs:45:11
   |
 LL |     asm!("li x17, 0");
   |           ^^^^^^^^^
@ -23,7 +23,7 @@ LL |     li x17, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
+  --> $DIR/riscv32e-registers.rs:48:11
   |
 LL |     asm!("li x18, 0");
   |           ^^^^^^^^^
@ -35,7 +35,7 @@ LL |     li x18, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
+  --> $DIR/riscv32e-registers.rs:51:11
   |
 LL |     asm!("li x19, 0");
   |           ^^^^^^^^^
@ -47,7 +47,7 @@ LL |     li x19, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
+  --> $DIR/riscv32e-registers.rs:54:11
   |
 LL |     asm!("li x20, 0");
   |           ^^^^^^^^^
@ -59,7 +59,7 @@ LL |     li x20, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
+  --> $DIR/riscv32e-registers.rs:57:11
   |
 LL |     asm!("li x21, 0");
   |           ^^^^^^^^^
@ -71,7 +71,7 @@ LL |     li x21, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
+  --> $DIR/riscv32e-registers.rs:60:11
   |
 LL |     asm!("li x22, 0");
   |           ^^^^^^^^^
@ -83,7 +83,7 @@ LL |     li x22, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
+  --> $DIR/riscv32e-registers.rs:63:11
   |
 LL |     asm!("li x23, 0");
   |           ^^^^^^^^^
@ -95,7 +95,7 @@ LL |     li x23, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
+  --> $DIR/riscv32e-registers.rs:66:11
   |
 LL |     asm!("li x24, 0");
   |           ^^^^^^^^^
@ -107,7 +107,7 @@ LL |     li x24, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
+  --> $DIR/riscv32e-registers.rs:69:11
   |
 LL |     asm!("li x25, 0");
   |           ^^^^^^^^^
@ -119,7 +119,7 @@ LL |     li x25, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
+  --> $DIR/riscv32e-registers.rs:72:11
   |
 LL |     asm!("li x26, 0");
   |           ^^^^^^^^^
@ -131,7 +131,7 @@ LL |     li x26, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
+  --> $DIR/riscv32e-registers.rs:75:11
   |
 LL |     asm!("li x27, 0");
   |           ^^^^^^^^^
@ -143,7 +143,7 @@ LL |     li x27, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
+  --> $DIR/riscv32e-registers.rs:78:11
   |
 LL |     asm!("li x28, 0");
   |           ^^^^^^^^^
@ -155,7 +155,7 @@ LL |     li x28, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
+  --> $DIR/riscv32e-registers.rs:81:11
   |
 LL |     asm!("li x29, 0");
   |           ^^^^^^^^^
@ -167,7 +167,7 @@ LL |     li x29, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
+  --> $DIR/riscv32e-registers.rs:84:11
   |
 LL |     asm!("li x30, 0");
   |           ^^^^^^^^^
@ -179,7 +179,7 @@ LL |     li x30, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
+  --> $DIR/riscv32e-registers.rs:87:11
   |
 LL |     asm!("li x31, 0");
   |           ^^^^^^^^^
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32e_llvm_18.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32e_llvm_18.stderr
@ -1,194 +0,0 @@
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
-   |
-LL |     asm!("li x16, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x16, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
-   |
-LL |     asm!("li x17, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x17, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
-   |
-LL |     asm!("li x18, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x18, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
-   |
-LL |     asm!("li x19, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x19, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
-   |
-LL |     asm!("li x20, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x20, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
-   |
-LL |     asm!("li x21, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x21, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
-   |
-LL |     asm!("li x22, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x22, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
-   |
-LL |     asm!("li x23, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x23, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
-   |
-LL |     asm!("li x24, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x24, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
-   |
-LL |     asm!("li x25, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x25, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
-   |
-LL |     asm!("li x26, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x26, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
-   |
-LL |     asm!("li x27, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x27, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
-   |
-LL |     asm!("li x28, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x28, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
-   |
-LL |     asm!("li x29, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x29, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
-   |
-LL |     asm!("li x30, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x30, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
-   |
-LL |     asm!("li x31, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x31, 0
-   |        ^
-
-error: aborting due to 16 previous errors
-
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32em.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32em.stderr
@ -1,5 +1,5 @@
 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
+  --> $DIR/riscv32e-registers.rs:42:11
   |
 LL |     asm!("li x16, 0");
   |           ^^^^^^^^^
@ -11,7 +11,7 @@ LL |     li x16, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
+  --> $DIR/riscv32e-registers.rs:45:11
   |
 LL |     asm!("li x17, 0");
   |           ^^^^^^^^^
@ -23,7 +23,7 @@ LL |     li x17, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
+  --> $DIR/riscv32e-registers.rs:48:11
   |
 LL |     asm!("li x18, 0");
   |           ^^^^^^^^^
@ -35,7 +35,7 @@ LL |     li x18, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
+  --> $DIR/riscv32e-registers.rs:51:11
   |
 LL |     asm!("li x19, 0");
   |           ^^^^^^^^^
@ -47,7 +47,7 @@ LL |     li x19, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
+  --> $DIR/riscv32e-registers.rs:54:11
   |
 LL |     asm!("li x20, 0");
   |           ^^^^^^^^^
@ -59,7 +59,7 @@ LL |     li x20, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
+  --> $DIR/riscv32e-registers.rs:57:11
   |
 LL |     asm!("li x21, 0");
   |           ^^^^^^^^^
@ -71,7 +71,7 @@ LL |     li x21, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
+  --> $DIR/riscv32e-registers.rs:60:11
   |
 LL |     asm!("li x22, 0");
   |           ^^^^^^^^^
@ -83,7 +83,7 @@ LL |     li x22, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
+  --> $DIR/riscv32e-registers.rs:63:11
   |
 LL |     asm!("li x23, 0");
   |           ^^^^^^^^^
@ -95,7 +95,7 @@ LL |     li x23, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
+  --> $DIR/riscv32e-registers.rs:66:11
   |
 LL |     asm!("li x24, 0");
   |           ^^^^^^^^^
@ -107,7 +107,7 @@ LL |     li x24, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
+  --> $DIR/riscv32e-registers.rs:69:11
   |
 LL |     asm!("li x25, 0");
   |           ^^^^^^^^^
@ -119,7 +119,7 @@ LL |     li x25, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
+  --> $DIR/riscv32e-registers.rs:72:11
   |
 LL |     asm!("li x26, 0");
   |           ^^^^^^^^^
@ -131,7 +131,7 @@ LL |     li x26, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
+  --> $DIR/riscv32e-registers.rs:75:11
   |
 LL |     asm!("li x27, 0");
   |           ^^^^^^^^^
@ -143,7 +143,7 @@ LL |     li x27, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
+  --> $DIR/riscv32e-registers.rs:78:11
   |
 LL |     asm!("li x28, 0");
   |           ^^^^^^^^^
@ -155,7 +155,7 @@ LL |     li x28, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
+  --> $DIR/riscv32e-registers.rs:81:11
   |
 LL |     asm!("li x29, 0");
   |           ^^^^^^^^^
@ -167,7 +167,7 @@ LL |     li x29, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
+  --> $DIR/riscv32e-registers.rs:84:11
   |
 LL |     asm!("li x30, 0");
   |           ^^^^^^^^^
@ -179,7 +179,7 @@ LL |     li x30, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
+  --> $DIR/riscv32e-registers.rs:87:11
   |
 LL |     asm!("li x31, 0");
   |           ^^^^^^^^^
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32em_llvm_18.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32em_llvm_18.stderr
@ -1,194 +0,0 @@
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
-   |
-LL |     asm!("li x16, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x16, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
-   |
-LL |     asm!("li x17, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x17, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
-   |
-LL |     asm!("li x18, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x18, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
-   |
-LL |     asm!("li x19, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x19, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
-   |
-LL |     asm!("li x20, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x20, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
-   |
-LL |     asm!("li x21, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x21, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
-   |
-LL |     asm!("li x22, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x22, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
-   |
-LL |     asm!("li x23, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x23, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
-   |
-LL |     asm!("li x24, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x24, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
-   |
-LL |     asm!("li x25, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x25, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
-   |
-LL |     asm!("li x26, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x26, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
-   |
-LL |     asm!("li x27, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x27, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
-   |
-LL |     asm!("li x28, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x28, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
-   |
-LL |     asm!("li x29, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x29, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
-   |
-LL |     asm!("li x30, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x30, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
-   |
-LL |     asm!("li x31, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x31, 0
-   |        ^
-
-error: aborting due to 16 previous errors
-
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32emc.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32emc.stderr
@ -1,5 +1,5 @@
 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
+  --> $DIR/riscv32e-registers.rs:42:11
   |
 LL |     asm!("li x16, 0");
   |           ^^^^^^^^^
@ -11,7 +11,7 @@ LL |     li x16, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
+  --> $DIR/riscv32e-registers.rs:45:11
   |
 LL |     asm!("li x17, 0");
   |           ^^^^^^^^^
@ -23,7 +23,7 @@ LL |     li x17, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
+  --> $DIR/riscv32e-registers.rs:48:11
   |
 LL |     asm!("li x18, 0");
   |           ^^^^^^^^^
@ -35,7 +35,7 @@ LL |     li x18, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
+  --> $DIR/riscv32e-registers.rs:51:11
   |
 LL |     asm!("li x19, 0");
   |           ^^^^^^^^^
@ -47,7 +47,7 @@ LL |     li x19, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
+  --> $DIR/riscv32e-registers.rs:54:11
   |
 LL |     asm!("li x20, 0");
   |           ^^^^^^^^^
@ -59,7 +59,7 @@ LL |     li x20, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
+  --> $DIR/riscv32e-registers.rs:57:11
   |
 LL |     asm!("li x21, 0");
   |           ^^^^^^^^^
@ -71,7 +71,7 @@ LL |     li x21, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
+  --> $DIR/riscv32e-registers.rs:60:11
   |
 LL |     asm!("li x22, 0");
   |           ^^^^^^^^^
@ -83,7 +83,7 @@ LL |     li x22, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
+  --> $DIR/riscv32e-registers.rs:63:11
   |
 LL |     asm!("li x23, 0");
   |           ^^^^^^^^^
@ -95,7 +95,7 @@ LL |     li x23, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
+  --> $DIR/riscv32e-registers.rs:66:11
   |
 LL |     asm!("li x24, 0");
   |           ^^^^^^^^^
@ -107,7 +107,7 @@ LL |     li x24, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
+  --> $DIR/riscv32e-registers.rs:69:11
   |
 LL |     asm!("li x25, 0");
   |           ^^^^^^^^^
@ -119,7 +119,7 @@ LL |     li x25, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
+  --> $DIR/riscv32e-registers.rs:72:11
   |
 LL |     asm!("li x26, 0");
   |           ^^^^^^^^^
@ -131,7 +131,7 @@ LL |     li x26, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
+  --> $DIR/riscv32e-registers.rs:75:11
   |
 LL |     asm!("li x27, 0");
   |           ^^^^^^^^^
@ -143,7 +143,7 @@ LL |     li x27, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
+  --> $DIR/riscv32e-registers.rs:78:11
   |
 LL |     asm!("li x28, 0");
   |           ^^^^^^^^^
@ -155,7 +155,7 @@ LL |     li x28, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
+  --> $DIR/riscv32e-registers.rs:81:11
   |
 LL |     asm!("li x29, 0");
   |           ^^^^^^^^^
@ -167,7 +167,7 @@ LL |     li x29, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
+  --> $DIR/riscv32e-registers.rs:84:11
   |
 LL |     asm!("li x30, 0");
   |           ^^^^^^^^^
@ -179,7 +179,7 @@ LL |     li x30, 0
   |        ^

 error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
+  --> $DIR/riscv32e-registers.rs:87:11
   |
 LL |     asm!("li x31, 0");
   |           ^^^^^^^^^
--- a/tests/ui/asm/riscv/riscv32e-registers.riscv32emc_llvm_18.stderr
+++ b/tests/ui/asm/riscv/riscv32e-registers.riscv32emc_llvm_18.stderr
@ -1,194 +0,0 @@
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:54:11
-   |
-LL |     asm!("li x16, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x16, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:57:11
-   |
-LL |     asm!("li x17, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x17, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:60:11
-   |
-LL |     asm!("li x18, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x18, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:63:11
-   |
-LL |     asm!("li x19, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x19, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:66:11
-   |
-LL |     asm!("li x20, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x20, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:69:11
-   |
-LL |     asm!("li x21, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x21, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:72:11
-   |
-LL |     asm!("li x22, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x22, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:75:11
-   |
-LL |     asm!("li x23, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x23, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:78:11
-   |
-LL |     asm!("li x24, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x24, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:81:11
-   |
-LL |     asm!("li x25, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x25, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:84:11
-   |
-LL |     asm!("li x26, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x26, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:87:11
-   |
-LL |     asm!("li x27, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x27, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:90:11
-   |
-LL |     asm!("li x28, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x28, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:93:11
-   |
-LL |     asm!("li x29, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x29, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:96:11
-   |
-LL |     asm!("li x30, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x30, 0
-   |        ^
-
-error: invalid operand for instruction
-  --> $DIR/riscv32e-registers.rs:99:11
-   |
-LL |     asm!("li x31, 0");
-   |           ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:5
-   |
-LL |     li x31, 0
-   |        ^
-
-error: aborting due to 16 previous errors
-
--- a/tests/ui/asm/riscv/riscv32e-registers.rs
+++ b/tests/ui/asm/riscv/riscv32e-registers.rs
@ -2,27 +2,15 @@
 //
 //@ add-core-stubs
 //@ build-fail
-//@ revisions: riscv32e riscv32em riscv32emc riscv32e_llvm_18 riscv32em_llvm_18 riscv32emc_llvm_18
+//@ revisions: riscv32e riscv32em riscv32emc
 //
 //@ compile-flags: --crate-type=rlib
 //@ [riscv32e] needs-llvm-components: riscv
 //@ [riscv32e] compile-flags: --target=riscv32e-unknown-none-elf
-//@ [riscv32e] min-llvm-version: 19
 //@ [riscv32em] needs-llvm-components: riscv
 //@ [riscv32em] compile-flags: --target=riscv32em-unknown-none-elf
-//@ [riscv32em] min-llvm-version: 19
 //@ [riscv32emc] needs-llvm-components: riscv
 //@ [riscv32emc] compile-flags: --target=riscv32emc-unknown-none-elf
-//@ [riscv32emc] min-llvm-version: 19
-//@ [riscv32e_llvm_18] needs-llvm-components: riscv
-//@ [riscv32e_llvm_18] compile-flags: --target=riscv32e-unknown-none-elf
-//@ [riscv32e_llvm_18] ignore-llvm-version: 19 - 99
-//@ [riscv32em_llvm_18] needs-llvm-components: riscv
-//@ [riscv32em_llvm_18] compile-flags: --target=riscv32em-unknown-none-elf
-//@ [riscv32em_llvm_18] ignore-llvm-version: 19 - 99
-//@ [riscv32emc_llvm_18] needs-llvm-components: riscv
-//@ [riscv32emc_llvm_18] compile-flags: --target=riscv32emc-unknown-none-elf
-//@ [riscv32emc_llvm_18] ignore-llvm-version: 19 - 99

 // Unlike bad-reg.rs, this tests if the assembler can reject invalid registers
 // usage in assembly code.
--- a/tests/ui/asm/x86_64/srcloc.old.stderr
+++ b/tests/ui/asm/x86_64/srcloc.old.stderr
@ -1,302 +0,0 @@
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:14:15
-   |
-LL |         asm!("invalid_instruction");
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction
-   |     ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:18:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:13
-   |
-LL |             invalid_instruction
-   |             ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:23:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:13
-   |
-LL |             invalid_instruction
-   |             ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:29:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:13
-   |
-LL |             invalid_instruction
-   |             ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:36:13
-   |
-LL |             invalid_instruction
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:13
-   |
-LL |             invalid_instruction
-   |             ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:41:14
-   |
-LL |         asm!(concat!("invalid", "_", "instruction"));
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction
-   |     ^^^^^^^^^^^^^^^^^^^
-
-warning: scale factor without index register is ignored
-  --> $DIR/srcloc.rs:44:15
-   |
-LL |         asm!("movaps %xmm3, (%esi, 2)", options(att_syntax));
-   |               ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:1:23
-   |
-LL |     movaps %xmm3, (%esi, 2)
-   |                          ^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:48:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction
-   |     ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:54:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction
-   | ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:61:14
-   |
-LL |             "invalid_instruction",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:1
-   |
-LL | invalid_instruction
-   | ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:68:13
-   |
-LL |             concat!("invalid", "_", "instruction"),
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction
-   | ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:75:13
-   |
-LL |             concat!("invalid", "_", "instruction"),
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction
-   | ^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:82:14
-   |
-LL |             "invalid_instruction1",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction1
-   |     ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:83:14
-   |
-LL |             "invalid_instruction2",
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction2
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:89:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction1
-   |     ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:89:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction2
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:98:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction1
-   |     ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:98:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction2
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction3'
-  --> $DIR/srcloc.rs:102:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:4:1
-   |
-LL | invalid_instruction3
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction4'
-  --> $DIR/srcloc.rs:102:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:5:1
-   |
-LL | invalid_instruction4
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:113:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:2:2
-   |
-LL |     invalid_instruction1
-   |     ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:113:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:3:1
-   |
-LL | invalid_instruction2
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction3'
-  --> $DIR/srcloc.rs:117:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:5:1
-   |
-LL | invalid_instruction3
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction4'
-  --> $DIR/srcloc.rs:117:13
-   |
-LL |             concat!(
-   |             ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:6:1
-   |
-LL | invalid_instruction4
-   | ^^^^^^^^^^^^^^^^^^^^
-
-error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:130:14
-   |
-LL |             "invalid_instruction"
-   |              ^
-   |
-note: instantiated into assembly here
-  --> <inline asm>:5:1
-   |
-LL | invalid_instruction
-   | ^^^^^^^^^^^^^^^^^^^
-
-error: aborting due to 24 previous errors; 1 warning emitted
-
--- a/tests/ui/asm/x86_64/srcloc.rs
+++ b/tests/ui/asm/x86_64/srcloc.rs
@ -1,9 +1,6 @@
-//@ revisions: old new
 //@ only-x86_64
 //@ build-fail
 //@ compile-flags: -Ccodegen-units=1
-//@[old] ignore-llvm-version: 19 - 99
-//@[new] min-llvm-version: 19

 use std::arch::asm;

--- a/tests/ui/asm/x86_64/srcloc.new.stderr
+++ b/tests/ui/asm/x86_64/srcloc.new.stderr
@ -1,5 +1,5 @@
 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:14:15
+  --> $DIR/srcloc.rs:11:15
   |
 LL |         asm!("invalid_instruction");
   |               ^^^^^^^^^^^^^^^^^^^
@ -11,7 +11,7 @@ LL |     invalid_instruction
   |     ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:18:13
+  --> $DIR/srcloc.rs:15:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -23,7 +23,7 @@ LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:23:13
+  --> $DIR/srcloc.rs:20:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -35,7 +35,7 @@ LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:29:13
+  --> $DIR/srcloc.rs:26:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -47,7 +47,7 @@ LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:36:13
+  --> $DIR/srcloc.rs:33:13
   |
 LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^
@ -59,7 +59,7 @@ LL |             invalid_instruction
   |             ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:41:14
+  --> $DIR/srcloc.rs:38:14
   |
 LL |         asm!(concat!("invalid", "_", "instruction"));
   |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -71,7 +71,7 @@ LL |     invalid_instruction
   |     ^^^^^^^^^^^^^^^^^^^

 warning: scale factor without index register is ignored
-  --> $DIR/srcloc.rs:44:15
+  --> $DIR/srcloc.rs:41:15
   |
 LL |         asm!("movaps %xmm3, (%esi, 2)", options(att_syntax));
   |               ^^^^^^^^^^^^^^^^^^^^^^^
@ -83,7 +83,7 @@ LL |     movaps %xmm3, (%esi, 2)
   |                          ^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:48:14
+  --> $DIR/srcloc.rs:45:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -95,7 +95,7 @@ LL |     invalid_instruction
   |     ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:54:14
+  --> $DIR/srcloc.rs:51:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -107,7 +107,7 @@ LL | invalid_instruction
   | ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:61:14
+  --> $DIR/srcloc.rs:58:14
   |
 LL |             "invalid_instruction",
   |              ^^^^^^^^^^^^^^^^^^^
@ -119,7 +119,7 @@ LL | invalid_instruction
   | ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:68:13
+  --> $DIR/srcloc.rs:65:13
   |
 LL |             concat!("invalid", "_", "instruction"),
   |             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -131,7 +131,7 @@ LL | invalid_instruction
   | ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:75:13
+  --> $DIR/srcloc.rs:72:13
   |
 LL |             concat!("invalid", "_", "instruction"),
   |             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -143,7 +143,7 @@ LL | invalid_instruction
   | ^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:82:14
+  --> $DIR/srcloc.rs:79:14
   |
 LL |             "invalid_instruction1",
   |              ^^^^^^^^^^^^^^^^^^^^
@ -155,7 +155,7 @@ LL |     invalid_instruction1
   |     ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:83:14
+  --> $DIR/srcloc.rs:80:14
   |
 LL |             "invalid_instruction2",
   |              ^^^^^^^^^^^^^^^^^^^^
@ -167,7 +167,7 @@ LL | invalid_instruction2
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:89:13
+  --> $DIR/srcloc.rs:86:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -182,7 +182,7 @@ LL |     invalid_instruction1
   |     ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:89:13
+  --> $DIR/srcloc.rs:86:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -197,7 +197,7 @@ LL | invalid_instruction2
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:98:13
+  --> $DIR/srcloc.rs:95:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -212,7 +212,7 @@ LL |     invalid_instruction1
   |     ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:98:13
+  --> $DIR/srcloc.rs:95:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -227,7 +227,7 @@ LL | invalid_instruction2
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction3'
-  --> $DIR/srcloc.rs:102:13
+  --> $DIR/srcloc.rs:99:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -242,7 +242,7 @@ LL | invalid_instruction3
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction4'
-  --> $DIR/srcloc.rs:102:13
+  --> $DIR/srcloc.rs:99:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -257,7 +257,7 @@ LL | invalid_instruction4
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction1'
-  --> $DIR/srcloc.rs:113:13
+  --> $DIR/srcloc.rs:110:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -272,7 +272,7 @@ LL |     invalid_instruction1
   |     ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction2'
-  --> $DIR/srcloc.rs:113:13
+  --> $DIR/srcloc.rs:110:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction1", "\n",
@ -287,7 +287,7 @@ LL | invalid_instruction2
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction3'
-  --> $DIR/srcloc.rs:117:13
+  --> $DIR/srcloc.rs:114:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -302,7 +302,7 @@ LL | invalid_instruction3
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction4'
-  --> $DIR/srcloc.rs:117:13
+  --> $DIR/srcloc.rs:114:13
   |
 LL | /             concat!(
 LL | |                 "invalid", "_", "instruction3", "\n",
@ -317,7 +317,7 @@ LL | invalid_instruction4
   | ^^^^^^^^^^^^^^^^^^^^

 error: invalid instruction mnemonic 'invalid_instruction'
-  --> $DIR/srcloc.rs:130:14
+  --> $DIR/srcloc.rs:127:14
   |
 LL |             "invalid_instruction"
   |              ^^^^^^^^^^^^^^^^^^^
--- a/tests/ui/instrument-coverage/mcdc-condition-limit.rs
+++ b/tests/ui/instrument-coverage/mcdc-condition-limit.rs
@ -1,5 +1,4 @@
 //@ edition: 2021
-//@ min-llvm-version: 19
 //@ revisions: good
 //@ check-pass
 //@ compile-flags: -Cinstrument-coverage -Zcoverage-options=mcdc -Zno-profiler-runtime