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Change capitalization of Spirv to SpirV

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This matches the capitalization of RiscV
This commit is contained in:
khyperia 2020-11-11 19:18:06 +01:00
parent f3441348e0
commit 0e34b73996
3 changed files with 22 additions and 22 deletions
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8
compiler/rustc_codegen_llvm/src/asm.rs
View File

@ -260,7 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
InlineAsmArch::Nvptx64 => {}
InlineAsmArch::Hexagon => {}
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
InlineAsmArch::Spirv => {}
InlineAsmArch::SpirV => {}
}
}
if !options.contains(InlineAsmOptions::NOMEM) {
@ -519,7 +519,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}
@ -584,7 +584,7 @@ fn modifier_to_llvm(
_ => unreachable!(),
},
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}
@ -626,7 +626,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
bug!("LLVM backend does not support SPIR-V")
}
}

30
compiler/rustc_target/src/asm/mod.rs
View File

@ -164,7 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass};
pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
@ -179,7 +179,7 @@ pub enum InlineAsmArch {
Hexagon,
Mips,
Mips64,
Spirv,
SpirV,
}
impl FromStr for InlineAsmArch {
@ -197,7 +197,7 @@ impl FromStr for InlineAsmArch {
"hexagon" => Ok(Self::Hexagon),
"mips" => Ok(Self::Mips),
"mips64" => Ok(Self::Mips64),
"spirv" => Ok(Self::Spirv),
"spirv" => Ok(Self::SpirV),
_ => Err(()),
}
}
@ -212,7 +212,7 @@ pub enum InlineAsmReg {
Nvptx(NvptxInlineAsmReg),
Hexagon(HexagonInlineAsmReg),
Mips(MipsInlineAsmReg),
Spirv(SpirvInlineAsmReg),
SpirV(SpirVInlineAsmReg),
}
impl InlineAsmReg {
@ -269,8 +269,8 @@ impl InlineAsmReg {
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
InlineAsmArch::Spirv => {
Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?)
InlineAsmArch::SpirV => {
Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?)
}
})
}
@ -314,7 +314,7 @@ pub enum InlineAsmRegClass {
Nvptx(NvptxInlineAsmRegClass),
Hexagon(HexagonInlineAsmRegClass),
Mips(MipsInlineAsmRegClass),
Spirv(SpirvInlineAsmRegClass),
SpirV(SpirVInlineAsmRegClass),
}
impl InlineAsmRegClass {
@ -327,7 +327,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.name(),
Self::Hexagon(r) => r.name(),
Self::Mips(r) => r.name(),
Self::Spirv(r) => r.name(),
Self::SpirV(r) => r.name(),
}
}
@ -343,7 +343,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv),
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
}
}
@ -366,7 +366,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
Self::Hexagon(r) => r.suggest_modifier(arch, ty),
Self::Mips(r) => r.suggest_modifier(arch, ty),
Self::Spirv(r) => r.suggest_modifier(arch, ty),
Self::SpirV(r) => r.suggest_modifier(arch, ty),
}
}
@ -385,7 +385,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.default_modifier(arch),
Self::Hexagon(r) => r.default_modifier(arch),
Self::Mips(r) => r.default_modifier(arch),
Self::Spirv(r) => r.default_modifier(arch),
Self::SpirV(r) => r.default_modifier(arch),
}
}
@ -403,7 +403,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.supported_types(arch),
Self::Hexagon(r) => r.supported_types(arch),
Self::Mips(r) => r.supported_types(arch),
Self::Spirv(r) => r.supported_types(arch),
Self::SpirV(r) => r.supported_types(arch),
}
}
@ -428,7 +428,7 @@ impl InlineAsmRegClass {
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
}
InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?),
InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
})
})
}
@ -444,7 +444,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.valid_modifiers(arch),
Self::Hexagon(r) => r.valid_modifiers(arch),
Self::Mips(r) => r.valid_modifiers(arch),
Self::Spirv(r) => r.valid_modifiers(arch),
Self::SpirV(r) => r.valid_modifiers(arch),
}
}
}
@ -587,7 +587,7 @@ pub fn allocatable_registers(
mips::fill_reg_map(arch, has_feature, target, &mut map);
map
}
InlineAsmArch::Spirv => {
InlineAsmArch::SpirV => {
let mut map = spirv::regclass_map();
spirv::fill_reg_map(arch, has_feature, target, &mut map);
map

6
compiler/rustc_target/src/asm/spirv.rs
View File

@ -2,12 +2,12 @@ use super::{InlineAsmArch, InlineAsmType};
use rustc_macros::HashStable_Generic;
def_reg_class! {
Spirv SpirvInlineAsmRegClass {
SpirV SpirVInlineAsmRegClass {
reg,
}
}
impl SpirvInlineAsmRegClass {
impl SpirVInlineAsmRegClass {
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
&[]
}
@ -42,5 +42,5 @@ impl SpirvInlineAsmRegClass {
def_regs! {
// SPIR-V is SSA-based, it does not have registers.
Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {}
SpirV SpirVInlineAsmReg SpirVInlineAsmRegClass {}
}