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Rollup merge of #118704 - esp-rs:rv32-tier-2, r=davidtwco

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Promote `riscv32{im|imafc}` targets to tier 2

Pending the approval of [the MCP](https://github.com/rust-lang/compiler-team/issues/701).
This commit is contained in:
Matthias Krüger 2024-01-04 15:33:57 +01:00 committed by GitHub
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4
src/doc/rustc/src/platform-support.md
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@ -161,7 +161,9 @@ target | std | notes
[`nvptx64-nvidia-cuda`](platform-support/nvptx64-nvidia-cuda.md) | * | --emit=asm generates PTX code that [runs on NVIDIA GPUs]
[`riscv32imac-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAC ISA)
[`riscv32i-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32I ISA)
[`riscv32im-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | | Bare RISC-V (RV32IM ISA)
[`riscv32imc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMC ISA)
[`riscv32imafc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAFC ISA)
`riscv64gc-unknown-none-elf` | * | Bare RISC-V (RV64IMAFDC ISA)
`riscv64imac-unknown-none-elf` | * | Bare RISC-V (RV64IMAC ISA)
`sparc64-unknown-linux-gnu` | ✓ | SPARC Linux (kernel 4.4, glibc 2.23)
@ -318,8 +320,6 @@ target | std | host | notes
[`powerpc64-ibm-aix`](platform-support/aix.md) | ? | | 64-bit AIX (7.2 and newer)
`riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33)
`riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl + RISCV32 support patches)
[`riscv32imafc-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | Bare RISC-V (RV32IMAFC ISA)
[`riscv32im-unknown-none-elf`](platform-support/riscv32imac-unknown-none-elf.md) | * | | Bare RISC-V (RV32IM ISA)
[`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA)
[`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF
[`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF

8
src/doc/rustc/src/platform-support/riscv32imac-unknown-none-elf.md
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@ -1,6 +1,6 @@
# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf`
**Tier: 2/3**
**Tier: 2**
Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs.
@ -24,11 +24,11 @@ This target is included in Rust and can be installed via `rustup`.
## Testing
This is a cross-compiled no-std target, which must be run either in a simulator
This is a cross-compiled `no-std` target, which must be run either in a simulator
or by programming them onto suitable hardware. It is not possible to run the
Rust testsuite on this target.
Rust test-suite on this target.
## Cross-compilation toolchains and C code
This target supports C code. If interlinking with C or C++, you may need to use
riscv64-unknown-elf-gcc as a linker instead of rust-lld.
`riscv64-unknown-elf-gcc` as a linker instead of `rust-lld`.