Add is_riscv_feature_detected!; modify impl of hint::spin_loop

Update library/core/src/hint.rs

Co-authored-by: Amanieu d'Antras <amanieu@gmail.com>

Remove redundant config gate

library/core/src/hint.rs

@@ -123,6 +123,21 @@ pub fn spin_loop() {
         }
     }
 
+    // RISC-V platform spin loop hint implementation
+    {
+        // RISC-V RV32 and RV64 share the same PAUSE instruction, but they are located in different
+        // modules in `core::arch`.
+        // In this case, here we call `pause` function in each core arch module.
+        #[cfg(target_arch = "riscv32")]
+        {
+            crate::arch::riscv32::pause();
+        }
+        #[cfg(target_arch = "riscv64")]
+        {
+            crate::arch::riscv64::pause();
+        }
+    }
+
     #[cfg(any(target_arch = "aarch64", all(target_arch = "arm", target_feature = "v6")))]
     {
         #[cfg(target_arch = "aarch64")]
@@ -137,11 +152,6 @@ pub fn spin_loop() {
             unsafe { crate::arch::arm::__yield() };
         }
     }
-
-    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-    {
-        crate::arch::riscv::pause();
-    }
 }
 
 /// An identity function that *__hints__* to the compiler to be maximally pessimistic about what

library/std/src/lib.rs

@@ -556,6 +556,7 @@ pub use std_detect::*;
 pub use std_detect::{
     is_aarch64_feature_detected, is_arm_feature_detected, is_mips64_feature_detected,
     is_mips_feature_detected, is_powerpc64_feature_detected, is_powerpc_feature_detected,
+    is_riscv_feature_detected,
 };
 
 // Re-export macros defined in libcore.

library/stdarch

@@ -1 +1 @@
-Subproject commit 0716b22e902207efabe46879cbf28d0189ab7924
+Subproject commit 2adc17a5442614dbe34626fdd9b32de7c07b8086