2020-09-23 13:13:49 +00:00
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//! Emulate LLVM intrinsics
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2019-07-30 12:37:20 +00:00
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use crate::intrinsics::*;
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2019-08-31 17:28:09 +00:00
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use crate::prelude::*;
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2019-07-28 07:54:57 +00:00
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2020-03-31 11:20:19 +00:00
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use rustc_middle::ty::subst::SubstsRef;
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2019-07-28 07:54:57 +00:00
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2020-03-27 11:14:45 +00:00
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pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
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2021-03-05 18:12:59 +00:00
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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2019-07-28 07:54:57 +00:00
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intrinsic: &str,
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2022-02-23 10:49:34 +00:00
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_substs: SubstsRef<'tcx>,
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2019-07-28 09:24:33 +00:00
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args: &[mir::Operand<'tcx>],
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2019-07-28 07:54:57 +00:00
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destination: Option<(CPlace<'tcx>, BasicBlock)>,
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) {
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2020-09-26 09:48:26 +00:00
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let ret = destination.unwrap().0;
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2019-07-29 10:43:24 +00:00
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2019-07-30 12:37:20 +00:00
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intrinsic_match! {
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2022-02-23 10:49:34 +00:00
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fx, intrinsic, args,
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2019-07-29 10:43:24 +00:00
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_ => {
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fx.tcx.sess.warn(&format!("unsupported llvm intrinsic {}; replacing with trap", intrinsic));
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crate::trap::trap_unimplemented(fx, intrinsic);
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};
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2019-07-29 10:50:20 +00:00
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// Used by `_mm_movemask_epi8` and `_mm256_movemask_epi8`
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2021-04-30 12:49:58 +00:00
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"llvm.x86.sse2.pmovmskb.128" | "llvm.x86.avx2.pmovmskb" | "llvm.x86.sse2.movmsk.pd", (c a) {
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2020-12-27 09:30:38 +00:00
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let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
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let lane_ty = fx.clif_type(lane_ty).unwrap();
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2019-07-30 12:37:20 +00:00
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assert!(lane_count <= 32);
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2019-07-29 10:43:24 +00:00
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let mut res = fx.bcx.ins().iconst(types::I32, 0);
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2019-07-29 16:59:17 +00:00
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for lane in (0..lane_count).rev() {
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2019-07-29 10:43:24 +00:00
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let a_lane = a.value_field(fx, mir::Field::new(lane.try_into().unwrap())).load_scalar(fx);
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2019-07-30 12:37:20 +00:00
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// cast float to int
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let a_lane = match lane_ty {
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types::F32 => fx.bcx.ins().bitcast(types::I32, a_lane),
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types::F64 => fx.bcx.ins().bitcast(types::I64, a_lane),
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_ => a_lane,
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};
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// extract sign bit of an int
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let a_lane_sign = fx.bcx.ins().ushr_imm(a_lane, i64::from(lane_ty.bits() - 1));
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// shift sign bit into result
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let a_lane_sign = clif_intcast(fx, a_lane_sign, types::I32, false);
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2019-07-29 10:43:24 +00:00
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res = fx.bcx.ins().ishl_imm(res, 1);
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res = fx.bcx.ins().bor(res, a_lane_sign);
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}
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let res = CValue::by_val(res, fx.layout_of(fx.tcx.types.i32));
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ret.write_cvalue(fx, res);
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};
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2021-04-30 12:49:58 +00:00
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"llvm.x86.sse2.cmp.ps" | "llvm.x86.sse2.cmp.pd", (c x, c y, o kind) {
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2022-02-23 10:49:34 +00:00
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let kind = crate::constant::mir_operand_get_const_val(fx, kind).expect("llvm.x86.sse2.cmp.* kind not const");
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let flt_cc = match kind.try_to_bits(Size::from_bytes(1)).unwrap_or_else(|| panic!("kind not scalar: {:?}", kind)) {
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2019-07-30 12:37:20 +00:00
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0 => FloatCC::Equal,
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1 => FloatCC::LessThan,
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2 => FloatCC::LessThanOrEqual,
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7 => {
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unimplemented!("Compares corresponding elements in `a` and `b` to see if neither is `NaN`.");
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}
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3 => {
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unimplemented!("Compares corresponding elements in `a` and `b` to see if either is `NaN`.");
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}
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4 => FloatCC::NotEqual,
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5 => {
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unimplemented!("not less than");
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}
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6 => {
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unimplemented!("not less than or equal");
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}
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kind => unreachable!("kind {:?}", kind),
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};
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2022-02-23 10:49:34 +00:00
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simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, res_lane_ty, x_lane, y_lane| {
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let res_lane = match lane_ty.kind() {
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2019-07-30 12:37:20 +00:00
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ty::Float(_) => fx.bcx.ins().fcmp(flt_cc, x_lane, y_lane),
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2022-02-23 10:49:34 +00:00
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_ => unreachable!("{:?}", lane_ty),
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2019-07-30 12:37:20 +00:00
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};
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2022-02-23 10:49:34 +00:00
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bool_to_zero_or_max_uint(fx, res_lane_ty, res_lane)
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2019-07-30 12:37:20 +00:00
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});
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};
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2021-04-30 12:49:58 +00:00
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"llvm.x86.sse2.psrli.d", (c a, o imm8) {
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2020-08-15 18:55:03 +00:00
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let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8).expect("llvm.x86.sse2.psrli.d imm8 not const");
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2022-02-23 10:49:34 +00:00
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simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
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match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
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2020-08-15 18:55:03 +00:00
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imm8 if imm8 < 32 => fx.bcx.ins().ushr_imm(lane, i64::from(imm8 as u8)),
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_ => fx.bcx.ins().iconst(types::I32, 0),
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2022-02-23 10:49:34 +00:00
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}
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2020-08-15 18:55:03 +00:00
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});
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};
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2021-04-30 12:49:58 +00:00
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"llvm.x86.sse2.pslli.d", (c a, o imm8) {
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2020-08-15 18:55:03 +00:00
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let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8).expect("llvm.x86.sse2.psrli.d imm8 not const");
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2022-02-23 10:49:34 +00:00
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simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
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match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
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2020-08-15 18:55:03 +00:00
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imm8 if imm8 < 32 => fx.bcx.ins().ishl_imm(lane, i64::from(imm8 as u8)),
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_ => fx.bcx.ins().iconst(types::I32, 0),
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2022-02-23 10:49:34 +00:00
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}
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2020-08-15 18:55:03 +00:00
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});
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};
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2021-04-30 12:49:58 +00:00
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"llvm.x86.sse2.storeu.dq", (v mem_addr, c a) {
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2020-08-15 18:55:03 +00:00
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// FIXME correctly handle the unalignment
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let dest = CPlace::for_ptr(Pointer::new(mem_addr), a.layout());
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dest.write_cvalue(fx, a);
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};
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2021-07-07 09:14:20 +00:00
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"llvm.x86.addcarry.64", (v c_in, c a, c b) {
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llvm_add_sub(
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fx,
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BinOp::Add,
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ret,
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c_in,
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a,
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b
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);
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};
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"llvm.x86.subborrow.64", (v b_in, c a, c b) {
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llvm_add_sub(
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fx,
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BinOp::Sub,
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ret,
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b_in,
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a,
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b
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);
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};
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2019-07-29 10:43:24 +00:00
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}
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2019-07-28 07:54:57 +00:00
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2022-03-20 15:55:21 +00:00
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let dest = destination.expect("all llvm intrinsics used by stdlib should return").1;
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let ret_block = fx.get_block(dest);
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fx.bcx.ins().jump(ret_block, &[]);
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2019-07-28 07:54:57 +00:00
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}
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2019-07-28 08:24:57 +00:00
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// llvm.x86.avx2.vperm2i128
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// llvm.x86.ssse3.pshuf.b.128
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// llvm.x86.avx2.pshuf.b
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// llvm.x86.avx2.psrli.w
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// llvm.x86.sse2.psrli.w
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2021-07-07 09:14:20 +00:00
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fn llvm_add_sub<'tcx>(
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fx: &mut FunctionCx<'_, '_, 'tcx>,
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bin_op: BinOp,
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ret: CPlace<'tcx>,
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cb_in: Value,
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a: CValue<'tcx>,
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b: CValue<'tcx>,
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) {
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assert_eq!(
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a.layout().ty,
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fx.tcx.types.u64,
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"llvm.x86.addcarry.64/llvm.x86.subborrow.64 second operand must be u64"
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);
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assert_eq!(
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b.layout().ty,
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fx.tcx.types.u64,
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"llvm.x86.addcarry.64/llvm.x86.subborrow.64 third operand must be u64"
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);
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// c + carry -> c + first intermediate carry or borrow respectively
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let int0 = crate::num::codegen_checked_int_binop(fx, bin_op, a, b);
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let c = int0.value_field(fx, mir::Field::new(0));
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let cb0 = int0.value_field(fx, mir::Field::new(1)).load_scalar(fx);
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// c + carry -> c + second intermediate carry or borrow respectively
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let cb_in_as_u64 = fx.bcx.ins().uextend(types::I64, cb_in);
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let cb_in_as_u64 = CValue::by_val(cb_in_as_u64, fx.layout_of(fx.tcx.types.u64));
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let int1 = crate::num::codegen_checked_int_binop(fx, bin_op, c, cb_in_as_u64);
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let (c, cb1) = int1.load_scalar_pair(fx);
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// carry0 | carry1 -> carry or borrow respectively
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let cb_out = fx.bcx.ins().bor(cb0, cb1);
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let layout = fx.layout_of(fx.tcx.mk_tup([fx.tcx.types.u8, fx.tcx.types.u64].iter()));
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let val = CValue::by_val_pair(cb_out, c, layout);
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ret.write_cvalue(fx, val);
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}
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