2019-02-27 22:31:30 +00:00
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// assembly-output: ptx-linker
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// compile-flags: --crate-type cdylib
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// only-nvptx64
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2019-06-12 21:09:08 +00:00
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// ignore-nvptx64
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2019-02-27 22:31:30 +00:00
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#![feature(abi_ptx, core_intrinsics)]
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#![no_std]
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use core::intrinsics::*;
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// aux-build: breakpoint-panic-handler.rs
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extern crate breakpoint_panic_handler;
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// Currently, LLVM NVPTX backend can only emit atomic instructions with
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// `relaxed` (PTX default) ordering. But it's also useful to make sure
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// the backend won't fail with other orders. Apparently, the backend
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// doesn't support fences as well. As a workaround `llvm.nvvm.membar.*`
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// could work, and perhaps on the long run, all the atomic operations
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// should rather be provided by `core::arch::nvptx`.
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// Also, PTX ISA doesn't have atomic `load`, `store` and `nand`.
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// FIXME(denzp): add tests for `core::sync::atomic::*`.
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#[no_mangle]
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pub unsafe extern "ptx-kernel" fn atomics_kernel(a: *mut u32) {
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// CHECK: atom.global.and.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.and.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_and(a, 1);
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atomic_and_relaxed(a, 1);
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// CHECK: atom.global.cas.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1, 2;
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// CHECK: atom.global.cas.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1, 2;
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atomic_cxchg(a, 1, 2);
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atomic_cxchg_relaxed(a, 1, 2);
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// CHECK: atom.global.max.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.max.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_max(a, 1);
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atomic_max_relaxed(a, 1);
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// CHECK: atom.global.min.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.min.s32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_min(a, 1);
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atomic_min_relaxed(a, 1);
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// CHECK: atom.global.or.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.or.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_or(a, 1);
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atomic_or_relaxed(a, 1);
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// CHECK: atom.global.max.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.max.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_umax(a, 1);
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atomic_umax_relaxed(a, 1);
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// CHECK: atom.global.min.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.min.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_umin(a, 1);
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atomic_umin_relaxed(a, 1);
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// CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_xadd(a, 1);
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atomic_xadd_relaxed(a, 1);
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// CHECK: atom.global.exch.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.exch.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_xchg(a, 1);
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atomic_xchg_relaxed(a, 1);
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// CHECK: atom.global.xor.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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// CHECK: atom.global.xor.b32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], 1;
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atomic_xor(a, 1);
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atomic_xor_relaxed(a, 1);
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// CHECK: mov.u32 %[[sub_0_arg:r[0-9]+]], 100;
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// CHECK: neg.s32 temp, %[[sub_0_arg]];
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// CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], temp;
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atomic_xsub(a, 100);
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// CHECK: mov.u32 %[[sub_1_arg:r[0-9]+]], 200;
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// CHECK: neg.s32 temp, %[[sub_1_arg]];
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// CHECK: atom.global.add.u32 %{{r[0-9]+}}, [%{{rd[0-9]+}}], temp;
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atomic_xsub_relaxed(a, 200);
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}
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