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5f90d90447
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter, and language server. Signed-off-by: Henner Zeller <h.zeller@acm.org>
86 lines
2.5 KiB
Nix
86 lines
2.5 KiB
Nix
{ lib
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, stdenv
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, fetchFromGitHub
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, buildBazelPackage
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, bazel_4
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, flex
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, bison
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, python3
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}:
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buildBazelPackage rec {
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pname = "verible";
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version = "0.0-2172-g238b6df6";
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# These environment variables are read in bazel/build-version.py to create
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# a build string. Otherwise it would attempt to extract it from .git/.
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GIT_DATE = "2022-08-08";
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GIT_VERSION = version;
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src = fetchFromGitHub {
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owner = "chipsalliance";
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repo = "verible";
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rev = "v${version}";
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sha256 = "sha256-iOJhdbipuqqBiYGgk95d1c8bEK6Z16l16GuzYCQRc2g=";
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};
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patches = [
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# Patch WORKSPACE file to not include windows-related dependencies,
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# as they are removed by bazel, breaking the fixed output derivation
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# TODO: fix upstream
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./remove-unused-deps.patch
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];
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bazelFlags = [ "--//bazel:use_local_flex_bison" ];
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fetchAttrs = {
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# Fixed output derivation hash after bazel fetch
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sha256 = "sha256-XoLdlEeoDJlyWlnXZADHOKu06zKHgHJfgey8UhOt+LM=";
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};
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nativeBuildInputs = [
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flex # We use local flex and bison as WORKSPACE sources fail
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bison # .. to compile with newer glibc
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python3
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];
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postPatch = ''
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patchShebangs bazel/build-version.py \
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common/util/create_version_header.sh \
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common/parser/move_yacc_stack_symbols.sh \
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common/parser/record_syntax_error.sh
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'';
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removeRulesCC = false;
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bazelTarget = ":install-binaries";
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bazelBuildFlags = [
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"-c opt"
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];
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buildAttrs = {
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installPhase = ''
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mkdir -p "$out/bin"
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install bazel-bin/common/tools/verible-patch-tool "$out/bin"
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V_TOOLS_DIR=bazel-bin/verilog/tools
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install $V_TOOLS_DIR/diff/verible-verilog-diff "$out/bin"
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install $V_TOOLS_DIR/formatter/verible-verilog-format "$out/bin"
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install $V_TOOLS_DIR/kythe/verible-verilog-kythe-extractor "$out/bin"
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install $V_TOOLS_DIR/lint/verible-verilog-lint "$out/bin"
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install $V_TOOLS_DIR/ls/verible-verilog-ls "$out/bin"
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install $V_TOOLS_DIR/obfuscator/verible-verilog-obfuscate "$out/bin"
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install $V_TOOLS_DIR/preprocessor/verible-verilog-preprocessor "$out/bin"
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install $V_TOOLS_DIR/project/verible-verilog-project "$out/bin"
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install $V_TOOLS_DIR/syntax/verible-verilog-syntax "$out/bin"
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'';
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};
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meta = with lib; {
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homepage = "https://github.com/chipsalliance/verible";
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description = "Suite of SystemVerilog developer tools. Including a style-linter, indexer, formatter, and language server.";
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license = licenses.asl20;
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platforms = platforms.linux;
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maintainers = with maintainers; [ hzeller ];
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};
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}
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