Henner Zeller 5f90d90447 verible: init at 0.0-2172-g238b6df6 ... Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter, and language server. Signed-off-by: Henner Zeller <h.zeller@acm.org>		2022-08-28 16:35:55 -07:00
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default.nix
remove-unused-deps.patch