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Merge #142792: gcc9: 9.3.0 -> 9.4.0 (into staging)
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Vladimír Čunát
commit
d71611fb72
@ -1,261 +0,0 @@
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From 6001db79c477b03eacc7e7049560921fb54b7845 Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Mon, 7 Sep 2020 20:15:36 +0100
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Subject: [PATCH] lra: Avoid cycling on certain subreg reloads [PR96796]
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This PR is about LRA cycling for a reload of the form:
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----------------------------------------------------------------------------
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Changing pseudo 196 in operand 1 of insn 103 on equiv [r105:DI*0x8+r140:DI]
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Creating newreg=287, assigning class ALL_REGS to slow/invalid mem r287
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Creating newreg=288, assigning class ALL_REGS to slow/invalid mem r288
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103: r203:SI=r288:SI<<0x1+r196:DI#0
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REG_DEAD r196:DI
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Inserting slow/invalid mem reload before:
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316: r287:DI=[r105:DI*0x8+r140:DI]
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317: r288:SI=r287:DI#0
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----------------------------------------------------------------------------
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The problem is with r287. We rightly give it a broad starting class of
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POINTER_AND_FP_REGS (reduced from ALL_REGS by preferred_reload_class).
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However, we never make forward progress towards narrowing it down to
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a specific choice of class (POINTER_REGS or FP_REGS).
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I think in practice we rely on two things to narrow a reload pseudo's
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class down to a specific choice:
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(1) a restricted class is specified when the pseudo is created
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This happens for input address reloads, where the class is taken
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from the target's chosen base register class. It also happens
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for simple REG reloads, where the class is taken from the chosen
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alternative's constraints.
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(2) uses of the reload pseudo as a direct input operand
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In this case get_reload_reg tries to reuse the existing register
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and narrow its class, instead of creating a new reload pseudo.
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However, neither occurs here. As described above, r287 rightly
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starts out with a wide choice of class, ultimately derived from
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ALL_REGS, so we don't get (1). And as the comments in the PR
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explain, r287 is never used as an input reload, only the subreg is,
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so we don't get (2):
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----------------------------------------------------------------------------
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Choosing alt 13 in insn 317: (0) r (1) w {*movsi_aarch64}
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Creating newreg=291, assigning class FP_REGS to r291
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317: r288:SI=r291:SI
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Inserting insn reload before:
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320: r291:SI=r287:DI#0
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----------------------------------------------------------------------------
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IMO, in this case we should rely on the reload of r316 to narrow
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down the class of r278. Currently we do:
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----------------------------------------------------------------------------
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Choosing alt 7 in insn 316: (0) r (1) m {*movdi_aarch64}
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Creating newreg=289 from oldreg=287, assigning class GENERAL_REGS to r289
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316: r289:DI=[r105:DI*0x8+r140:DI]
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Inserting insn reload after:
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318: r287:DI=r289:DI
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---------------------------------------------------
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i.e. we create a new pseudo register r289 and give *that* pseudo
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GENERAL_REGS instead. This is because get_reload_reg only narrows
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down the existing class for OP_IN and OP_INOUT, not OP_OUT.
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But if we have a reload pseudo in a reload instruction and have chosen
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a specific class for the reload pseudo, I think we should simply install
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it for OP_OUT reloads too, if the class is a subset of the existing class.
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We will need to pick such a register whatever happens (for r289 in the
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example above). And as explained in the PR, doing this actually avoids
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an unnecessary move via the FP registers too.
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The patch is quite aggressive in that it does this for all reload
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pseudos in all reload instructions. I wondered about reusing the
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condition for a reload move in in_class_p:
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INSN_UID (curr_insn) >= new_insn_uid_start
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&& curr_insn_set != NULL
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&& ((OBJECT_P (SET_SRC (curr_insn_set))
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&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
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|| (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
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&& OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
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&& ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
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but I can't really justify that on first principles. I think we
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should apply the rule consistently until we have a specific reason
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for doing otherwise.
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gcc/
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PR rtl-optimization/96796
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* lra-constraints.c (in_class_p): Add a default-false
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allow_all_reload_class_changes_p parameter. Do not treat
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reload moves specially when the parameter is true.
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(get_reload_reg): Try to narrow the class of an existing OP_OUT
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reload if we're reloading a reload pseudo in a reload instruction.
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gcc/testsuite/
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PR rtl-optimization/96796
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* gcc.c-torture/compile/pr96796.c: New test.
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---
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gcc/lra-constraints.c | 54 ++++++++++++++----
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gcc/testsuite/gcc.c-torture/compile/pr96796.c | 55 +++++++++++++++++++
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2 files changed, 99 insertions(+), 10 deletions(-)
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create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr96796.c
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diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
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index 580da9c3ed6..161b721efb1 100644
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--- a/gcc/lra-constraints.c
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+++ b/gcc/lra-constraints.c
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@@ -236,12 +236,17 @@ get_reg_class (int regno)
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CL. Use elimination first if REG is a hard register. If REG is a
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reload pseudo created by this constraints pass, assume that it will
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be allocated a hard register from its allocno class, but allow that
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- class to be narrowed to CL if it is currently a superset of CL.
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+ class to be narrowed to CL if it is currently a superset of CL and
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+ if either:
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+
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+ - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
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+ - the instruction we're processing is not a reload move.
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If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
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REGNO (reg), or NO_REGS if no change in its class was needed. */
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static bool
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-in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
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+in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class,
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+ bool allow_all_reload_class_changes_p = false)
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{
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enum reg_class rclass, common_class;
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machine_mode reg_mode;
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@@ -266,7 +271,8 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
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typically moves that have many alternatives, and restricting
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reload pseudos for one alternative may lead to situations
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where other reload pseudos are no longer allocatable. */
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- || (INSN_UID (curr_insn) >= new_insn_uid_start
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+ || (!allow_all_reload_class_changes_p
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+ && INSN_UID (curr_insn) >= new_insn_uid_start
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&& curr_insn_set != NULL
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&& ((OBJECT_P (SET_SRC (curr_insn_set))
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&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
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@@ -598,13 +604,12 @@ canonicalize_reload_addr (rtx addr)
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return addr;
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}
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-/* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
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- created input reload pseudo (only if TYPE is not OP_OUT). Don't
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- reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
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- wrapped up in SUBREG. The result pseudo is returned through
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- RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
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- reused the already created input reload pseudo. Use TITLE to
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- describe new registers for debug purposes. */
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+/* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse an existing
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+ reload pseudo. Don't reuse an existing reload pseudo if IN_SUBREG_P
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+ is true and the reused pseudo should be wrapped up in a SUBREG.
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+ The result pseudo is returned through RESULT_REG. Return TRUE if we
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+ created a new pseudo, FALSE if we reused an existing reload pseudo.
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+ Use TITLE to describe new registers for debug purposes. */
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static bool
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get_reload_reg (enum op_type type, machine_mode mode, rtx original,
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enum reg_class rclass, bool in_subreg_p,
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@@ -616,6 +621,35 @@ get_reload_reg (enum op_type type, machine_mode mode, rtx original,
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if (type == OP_OUT)
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{
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+ /* Output reload registers tend to start out with a conservative
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+ choice of register class. Usually this is ALL_REGS, although
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+ a target might narrow it (for performance reasons) through
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+ targetm.preferred_reload_class. It's therefore quite common
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+ for a reload instruction to require a more restrictive class
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+ than the class that was originally assigned to the reload register.
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+
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+ In these situations, it's more efficient to refine the choice
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+ of register class rather than create a second reload register.
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+ This also helps to avoid cycling for registers that are only
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+ used by reload instructions. */
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+ if (REG_P (original)
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+ && (int) REGNO (original) >= new_regno_start
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+ && INSN_UID (curr_insn) >= new_insn_uid_start
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+ && in_class_p (original, rclass, &new_class, true))
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+ {
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+ unsigned int regno = REGNO (original);
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+ if (lra_dump_file != NULL)
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+ {
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+ fprintf (lra_dump_file, " Reuse r%d for output ", regno);
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+ dump_value_slim (lra_dump_file, original, 1);
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+ }
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+ if (new_class != lra_get_allocno_class (regno))
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+ lra_change_class (regno, new_class, ", change to", false);
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+ if (lra_dump_file != NULL)
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+ fprintf (lra_dump_file, "\n");
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+ *result_reg = original;
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+ return false;
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+ }
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*result_reg
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= lra_create_new_reg_with_unique_value (mode, original, rclass, title);
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return true;
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diff --git a/gcc/testsuite/gcc.c-torture/compile/pr96796.c b/gcc/testsuite/gcc.c-torture/compile/pr96796.c
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new file mode 100644
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index 00000000000..8808e62fe77
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--- /dev/null
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+++ b/gcc/testsuite/gcc.c-torture/compile/pr96796.c
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@@ -0,0 +1,55 @@
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+/* { dg-additional-options "-fcommon" } */
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+
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+struct S0 {
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+ signed f0 : 8;
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+ unsigned f1;
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+ unsigned f4;
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+};
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+struct S1 {
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+ long f3;
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+ char f4;
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+} g_3_4;
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+
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+int g_5, func_1_l_32, func_50___trans_tmp_31;
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+static struct S0 g_144, g_834, g_1255, g_1261;
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+
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+int g_273[120] = {};
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+int *g_555;
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+char **g_979;
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+static int g_1092_0;
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+static int g_1193;
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+int safe_mul_func_int16_t_s_s(int si1, int si2) { return si1 * si2; }
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+static struct S0 *func_50();
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+int func_1() { func_50(g_3_4, g_5, func_1_l_32, 8, 3); }
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+void safe_div_func_int64_t_s_s(int *);
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+void safe_mod_func_uint32_t_u_u(struct S0);
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+struct S0 *func_50(int p_51, struct S0 p_52, struct S1 p_53, int p_54,
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+ int p_55) {
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+ int __trans_tmp_30;
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+ char __trans_tmp_22;
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+ short __trans_tmp_19;
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+ long l_985_1;
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+ long l_1191[8];
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+ safe_div_func_int64_t_s_s(g_273);
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+ __builtin_printf((char*)g_1261.f4);
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+ safe_mod_func_uint32_t_u_u(g_834);
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+ g_144.f0 += 1;
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+ for (;;) {
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+ struct S1 l_1350 = {&l_1350};
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+ for (; p_53.f3; p_53.f3 -= 1)
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+ for (; g_1193 <= 2; g_1193 += 1) {
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+ __trans_tmp_19 = safe_mul_func_int16_t_s_s(l_1191[l_985_1 + p_53.f3],
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+ p_55 % (**g_979 = 10));
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+ __trans_tmp_22 = g_1255.f1 * p_53.f4;
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+ __trans_tmp_30 = __trans_tmp_19 + __trans_tmp_22;
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+ if (__trans_tmp_30)
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+ g_1261.f0 = p_51;
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+ else {
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+ g_1255.f0 = p_53.f3;
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+ int *l_1422 = g_834.f0 = g_144.f4 != (*l_1422)++ > 0 < 0 ^ 51;
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+ g_555 = ~0;
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+ g_1092_0 |= func_50___trans_tmp_31;
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+ }
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+ }
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+ }
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+}
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--
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2.18.4
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@ -63,17 +63,11 @@ with lib;
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with builtins;
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let majorVersion = "9";
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version = "${majorVersion}.3.0";
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version = "${majorVersion}.4.0";
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inherit (stdenv) buildPlatform hostPlatform targetPlatform;
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patches =
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# Fix ICE: Max. number of generated reload insns per insn is achieved (90)
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#
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# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96796
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#
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# This patch can most likely be removed by a post 9.3.0-release.
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[ ./avoid-cycling-subreg-reloads.patch ]
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patches = []
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++ optional (targetPlatform != hostPlatform) ../libstdc++-target.patch
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++ optional targetPlatform.isNetBSD ../libstdc++-netbsd-ctypes.patch
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++ optional noSysDirs ../no-sys-dirs.patch
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@ -87,9 +81,7 @@ let majorVersion = "9";
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++ optional (targetPlatform.libc == "musl" && targetPlatform.isPower) ../ppc-musl.patch
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# Obtain latest patch with ../update-mcfgthread-patches.sh
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++ optional (!crossStageStatic && targetPlatform.isMinGW) ./Added-mcf-thread-model-support-from-mcfgthread.patch
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++ [ ../libsanitizer-no-cyclades-9.patch ];
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++ optional (!crossStageStatic && targetPlatform.isMinGW) ./Added-mcf-thread-model-support-from-mcfgthread.patch;
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/* Cross-gcc settings (build == host != target) */
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crossMingw = targetPlatform != hostPlatform && targetPlatform.libc == "msvcrt";
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@ -106,7 +98,7 @@ stdenv.mkDerivation ({
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src = fetchurl {
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url = "mirror://gcc/releases/gcc-${version}/gcc-${version}.tar.xz";
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sha256 = "1la2yy27ziasyf0jvzk58y1i5b5bq2h176qil550bxhifs39gqbi";
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sha256 = "13l3p6g2krilaawbapmn9zmmrh3zdwc36mfr3msxfy038hps6pf9";
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};
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inherit patches;
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