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yosys: 2015.12.29 -> 2016.05.21
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@ -2,21 +2,21 @@
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stdenv.mkDerivation rec {
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name = "yosys-${version}";
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version = "2015.12.29";
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version = "2016.05.21";
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srcs = [
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(fetchFromGitHub {
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owner = "cliffordwolf";
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repo = "yosys";
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rev = "1d62f8710f04fec405ef79b9e9a4a031afcf7d42";
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sha256 = "0q1dk9in3gmrihb58pjckncx56lj7y4b6y34jgb68f0fh91fdvfx";
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rev = "8e9e793126a2772eed4b041bc60415943c71d5ee";
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sha256 = "1s0x7n7qh2qbfc0d7p4q10fvkr61jdqgyqzijr422rabh9zl4val";
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name = "yosys";
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})
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(fetchFromBitbucket {
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owner = "alanmi";
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repo = "abc";
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rev = "c3698e053a7a";
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sha256 = "05p0fvbr7xvb6w3d7j2r6gynr3ljb6r5q6jvn2zs3ysn2b003qwd";
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rev = "d9559ab";
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sha256 = "08far669khb65kfpqvjqmqln473j949ak07xibfdjdmiikcy533i";
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name = "abc";
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})
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];
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@ -37,7 +37,6 @@ stdenv.mkDerivation rec {
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Yosys is a framework for RTL synthesis tools. It currently has
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extensive Verilog-2005 support and provides a basic set of
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synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys C++
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