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lib/systems/architectures: add sapphirerapids/emeraldrapids
For reference: https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids https://www.phoronix.com/news/GCC-13-Initial-Emerald-Rapids https://www.phoronix.com/news/LLVM-Adds-Intel-Emerald-Rapids
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@ -26,6 +26,8 @@ rec {
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cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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sapphirerapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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emeraldrapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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# x86_64 AMD
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btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
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btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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@ -73,6 +75,8 @@ rec {
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cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake;
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emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids;
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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alderlake = [ ];
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@ -162,6 +162,8 @@ let
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tigerlake = versionAtLeast ccVersion "10.0";
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knm = versionAtLeast ccVersion "8.0";
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alderlake = versionAtLeast ccVersion "12.0";
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sapphirerapids = versionAtLeast ccVersion "11.0";
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emeraldrapids = versionAtLeast ccVersion "13.0";
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# AMD
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znver1 = true;
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@ -181,6 +183,8 @@ let
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icelake-server = versionAtLeast ccVersion "7.0";
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knm = versionAtLeast ccVersion "7.0";
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alderlake = versionAtLeast ccVersion "16.0";
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sapphirerapids = versionAtLeast ccVersion "12.0";
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emeraldrapids = versionAtLeast ccVersion "16.0";
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# AMD
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znver1 = versionAtLeast ccVersion "4.0";
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