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yosys: enable tests
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@ -2,6 +2,7 @@
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, pkgconfig, bison, flex
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, tcl, readline, libffi, python3
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, protobuf, zlib
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, verilog
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}:
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with builtins;
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@ -49,6 +50,7 @@ stdenv.mkDerivation rec {
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--replace 'LD = gcc' 'LD = $(CXX)' \
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--replace 'ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"' 'ABCMKARGS =' \
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--replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
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patchShebangs tests
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'';
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preBuild = ''
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@ -62,6 +64,13 @@ stdenv.mkDerivation rec {
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(cd misc && ${protobuf}/bin/protoc --cpp_out ../backends/protobuf/ ./yosys.proto)
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'';
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doCheck = true;
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checkInputs = [ verilog ];
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# checkPhase defaults to VERBOSE=y, which gets passed down to abc,
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# which then does $(VERBOSE)gcc, which then complains about not
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# being able to find ygcc. Life is pain.
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checkFlags = [ " " ];
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meta = {
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description = "Framework for RTL synthesis tools";
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longDescription = ''
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