mirror of
https://github.com/NixOS/nixpkgs.git
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61 lines
1.6 KiB
Nix
61 lines
1.6 KiB
Nix
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{ lib, stdenv, jre, setJavaClassPath, coursier, makeWrapper }:
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stdenv.mkDerivation rec {
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pname = "firrtl";
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version = "1.5.3";
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scalaVersion = "2.13"; # pin, for determinism
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deps = stdenv.mkDerivation {
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pname = "${pname}-deps";
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inherit version;
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nativeBuildInputs = [ coursier ];
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buildCommand = ''
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export COURSIER_CACHE=$(pwd)
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cs fetch edu.berkeley.cs:${pname}_${scalaVersion}:${version} > deps
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mkdir -p $out/share/java
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cp $(< deps) $out/share/java
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'';
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outputHashMode = "recursive";
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outputHash = "sha256-xy3zdJZk6Q2HbEn5tRQ9Z0AjyXEteXepoWDaATjiUUw=";
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};
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nativeBuildInputs = [ makeWrapper setJavaClassPath ];
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buildInputs = [ deps ];
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dontUnpack = true;
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installPhase = ''
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runHook preInstall
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makeWrapper ${jre}/bin/java $out/bin/${pname} \
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--add-flags "-cp $CLASSPATH firrtl.stage.FirrtlMain"
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runHook postInstall
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'';
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doInstallCheck = true;
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installCheckPhase = ''
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$out/bin/firrtl --firrtl-source "${''
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circuit test:
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module test:
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input a: UInt<8>
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input b: UInt<8>
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output o: UInt
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o <= add(a, not(b))
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''}" -o test.v
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cat test.v
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grep -qFe "module test" -e "endmodule" test.v
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'';
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meta = with lib; {
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description = "Flexible Intermediate Representation for RTL";
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longDescription = ''
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Firrtl is an intermediate representation (IR) for digital circuits
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designed as a platform for writing circuit-level transformations.
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'';
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homepage = "https://www.chisel-lang.org/firrtl/";
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license = licenses.asl20;
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maintainers = with maintainers; [ dtzWill ];
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};
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}
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