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42 lines
1.7 KiB
Makefile
42 lines
1.7 KiB
Makefile
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# These are the complete command lines we use to compile C and C++ files.
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# - $< is the source file.
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# - $1 is the object file to create.
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CC_CMD=$(CC) -o $1 -c $< $(CPPFLAGS) $(GLOBAL_CFLAGS) $(CFLAGS) $($1_CFLAGS) -MMD -MF $(call filename-to-dep,$1) -MP
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CXX_CMD=$(CXX) -o $1 -c $< $(CPPFLAGS) $(GLOBAL_CXXFLAGS_PCH) $(GLOBAL_CXXFLAGS) $(CXXFLAGS) $($1_CXXFLAGS) $(ERROR_SWITCH_ENUM) -MMD -MF $(call filename-to-dep,$1) -MP
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# We use COMPILE_COMMANDS_JSON_CMD to turn a compilation command (like CC_CMD
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# or CXX_CMD above) into a comple_commands.json file. We rely on bash native
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# word splitting to define the positional arguments.
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# - $< is the source file being compiled.
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COMPILE_COMMANDS_JSON_CMD=jq --null-input '{ directory: $$ENV.PWD, file: "$<", arguments: $$ARGS.positional }' --args --
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$(buildprefix)%.o: %.cc
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@mkdir -p "$(dir $@)"
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$(trace-cxx) $(call CXX_CMD,$@)
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$(buildprefix)%.o: %.cpp
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@mkdir -p "$(dir $@)"
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$(trace-cxx) $(call CXX_CMD,$@)
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$(buildprefix)%.o: %.c
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@mkdir -p "$(dir $@)"
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$(trace-cc) $(call CC_CMD,$@)
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# In the following we need to replace the .compile_commands.json extension in $@ with .o
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# to make the object file. This is needed because CC_CMD and CXX_CMD do further expansions
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# based on the object file name (i.e. *_CXXFLAGS and filename-to-dep).
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$(buildprefix)%.compile_commands.json: %.cc
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@mkdir -p "$(dir $@)"
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$(trace-jq) $(COMPILE_COMMANDS_JSON_CMD) $(call CXX_CMD,$(@:.compile_commands.json=.o)) > $@
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$(buildprefix)%.compile_commands.json: %.cpp
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@mkdir -p "$(dir $@)"
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$(trace-jq) $(COMPILE_COMMANDS_JSON_CMD) $(call CXX_CMD,$(@:.compile_commands.json=.o)) > $@
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$(buildprefix)%.compile_commands.json: %.c
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@mkdir -p "$(dir $@)"
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$(trace-jq) $(COMPILE_COMMANDS_JSON_CMD) $(call CC_CMD,$(@:.compile_commands.json=.o)) > $@
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