mirror of
https://github.com/embassy-rs/embassy.git
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256 lines
8.3 KiB
Rust
256 lines
8.3 KiB
Rust
use core::marker::PhantomData;
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use embedded_hal_async::spi::SpiDevice;
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use crate::chip::Chip;
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#[repr(u8)]
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enum Command {
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Open = 0x01,
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Send = 0x20,
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Receive = 0x40,
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}
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#[repr(u8)]
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enum Interrupt {
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Receive = 0b00100_u8,
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}
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/// Wiznet chip in MACRAW mode
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct WiznetDevice<C, SPI> {
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spi: SPI,
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_phantom: PhantomData<C>,
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}
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/// Error type when initializing a new Wiznet device
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pub enum InitError<SE> {
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/// Error occurred when sending or receiving SPI data
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SpiError(SE),
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/// The chip returned a version that isn't expected or supported
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InvalidChipVersion {
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/// The version that is supported
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expected: u8,
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/// The version that was returned by the chip
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actual: u8,
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},
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}
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impl<SE> From<SE> for InitError<SE> {
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fn from(e: SE) -> Self {
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InitError::SpiError(e)
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}
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}
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impl<SE> core::fmt::Debug for InitError<SE>
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where
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SE: core::fmt::Debug,
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{
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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match self {
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InitError::SpiError(e) => write!(f, "SpiError({:?})", e),
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InitError::InvalidChipVersion { expected, actual } => {
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write!(f, "InvalidChipVersion {{ expected: {}, actual: {} }}", expected, actual)
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}
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}
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}
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}
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#[cfg(feature = "defmt")]
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impl<SE> defmt::Format for InitError<SE>
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where
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SE: defmt::Format,
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{
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fn format(&self, f: defmt::Formatter) {
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match self {
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InitError::SpiError(e) => defmt::write!(f, "SpiError({})", e),
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InitError::InvalidChipVersion { expected, actual } => {
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defmt::write!(f, "InvalidChipVersion {{ expected: {}, actual: {} }}", expected, actual)
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}
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}
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}
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}
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impl<C: Chip, SPI: SpiDevice> WiznetDevice<C, SPI> {
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/// Create and initialize the driver
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pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<Self, InitError<SPI::Error>> {
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let mut this = Self {
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spi,
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_phantom: PhantomData,
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};
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// Reset device
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this.bus_write(C::COMMON_MODE, &[0x80]).await?;
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// Check the version of the chip
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let mut version = [0];
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this.bus_read(C::COMMON_VERSION, &mut version).await?;
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if version[0] != C::CHIP_VERSION {
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#[cfg(feature = "defmt")]
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defmt::error!("invalid chip version: {} (expected {})", version[0], C::CHIP_VERSION);
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return Err(InitError::InvalidChipVersion {
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actual: version[0],
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expected: C::CHIP_VERSION,
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});
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}
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// Enable interrupt pin
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this.bus_write(C::COMMON_SOCKET_INTR, &[0x01]).await?;
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// Enable receive interrupt
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this.bus_write(C::SOCKET_INTR_MASK, &[Interrupt::Receive as u8]).await?;
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// Set MAC address
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this.bus_write(C::COMMON_MAC, &mac_addr).await?;
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// Set the raw socket RX/TX buffer sizes.
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let buf_kbs = (C::BUF_SIZE / 1024) as u8;
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this.bus_write(C::SOCKET_TXBUF_SIZE, &[buf_kbs]).await?;
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this.bus_write(C::SOCKET_RXBUF_SIZE, &[buf_kbs]).await?;
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// MACRAW mode with MAC filtering.
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this.bus_write(C::SOCKET_MODE, &[C::SOCKET_MODE_VALUE]).await?;
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this.command(Command::Open).await?;
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Ok(this)
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}
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async fn bus_read(&mut self, address: C::Address, data: &mut [u8]) -> Result<(), SPI::Error> {
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C::bus_read(&mut self.spi, address, data).await
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}
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async fn bus_write(&mut self, address: C::Address, data: &[u8]) -> Result<(), SPI::Error> {
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C::bus_write(&mut self.spi, address, data).await
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}
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async fn reset_interrupt(&mut self, code: Interrupt) -> Result<(), SPI::Error> {
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let data = [code as u8];
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self.bus_write(C::SOCKET_INTR, &data).await
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}
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async fn get_tx_write_ptr(&mut self) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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self.bus_read(C::SOCKET_TX_DATA_WRITE_PTR, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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async fn set_tx_write_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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self.bus_write(C::SOCKET_TX_DATA_WRITE_PTR, &data).await
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}
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async fn get_rx_read_ptr(&mut self) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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self.bus_read(C::SOCKET_RX_DATA_READ_PTR, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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async fn set_rx_read_ptr(&mut self, ptr: u16) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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self.bus_write(C::SOCKET_RX_DATA_READ_PTR, &data).await
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}
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async fn command(&mut self, command: Command) -> Result<(), SPI::Error> {
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let data = [command as u8];
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self.bus_write(C::SOCKET_COMMAND, &data).await
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}
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async fn get_rx_size(&mut self) -> Result<u16, SPI::Error> {
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loop {
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// Wait until two sequential reads are equal
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let mut res0 = [0u8; 2];
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self.bus_read(C::SOCKET_RECVD_SIZE, &mut res0).await?;
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let mut res1 = [0u8; 2];
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self.bus_read(C::SOCKET_RECVD_SIZE, &mut res1).await?;
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if res0 == res1 {
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break Ok(u16::from_be_bytes(res0));
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}
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}
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}
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async fn get_tx_free_size(&mut self) -> Result<u16, SPI::Error> {
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let mut data = [0; 2];
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self.bus_read(C::SOCKET_TX_FREE_SIZE, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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/// Read bytes from the RX buffer.
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async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
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if C::AUTO_WRAP {
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self.bus_read(C::rx_addr(*read_ptr), buffer).await?;
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} else {
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let addr = *read_ptr % C::BUF_SIZE;
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if addr as usize + buffer.len() <= C::BUF_SIZE as usize {
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self.bus_read(C::rx_addr(addr), buffer).await?;
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} else {
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let n = C::BUF_SIZE - addr;
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self.bus_read(C::rx_addr(addr), &mut buffer[..n as usize]).await?;
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self.bus_read(C::rx_addr(0), &mut buffer[n as usize..]).await?;
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}
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}
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*read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
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Ok(())
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}
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/// Read an ethernet frame from the device. Returns the number of bytes read.
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pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
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let rx_size = self.get_rx_size().await? as usize;
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if rx_size == 0 {
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return Ok(0);
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}
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self.reset_interrupt(Interrupt::Receive).await?;
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let mut read_ptr = self.get_rx_read_ptr().await?;
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// First two bytes gives the size of the received ethernet frame
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let expected_frame_size: usize = {
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let mut frame_bytes = [0u8; 2];
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self.read_bytes(&mut read_ptr, &mut frame_bytes).await?;
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u16::from_be_bytes(frame_bytes) as usize - 2
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};
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// Read the ethernet frame
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self.read_bytes(&mut read_ptr, &mut frame[..expected_frame_size])
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.await?;
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// Register RX as completed
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self.set_rx_read_ptr(read_ptr).await?;
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self.command(Command::Receive).await?;
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Ok(expected_frame_size)
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}
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/// Write an ethernet frame to the device. Returns number of bytes written
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pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
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while self.get_tx_free_size().await? < frame.len() as u16 {}
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let write_ptr = self.get_tx_write_ptr().await?;
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if C::AUTO_WRAP {
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self.bus_write(C::tx_addr(write_ptr), frame).await?;
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} else {
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let addr = write_ptr % C::BUF_SIZE;
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if addr as usize + frame.len() <= C::BUF_SIZE as usize {
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self.bus_write(C::tx_addr(addr), frame).await?;
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} else {
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let n = C::BUF_SIZE - addr;
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self.bus_write(C::tx_addr(addr), &frame[..n as usize]).await?;
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self.bus_write(C::tx_addr(0), &frame[n as usize..]).await?;
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}
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}
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self.set_tx_write_ptr(write_ptr.wrapping_add(frame.len() as u16))
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.await?;
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self.command(Command::Send).await?;
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Ok(frame.len())
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}
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pub async fn is_link_up(&mut self) -> bool {
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let mut link = [0];
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self.bus_read(C::COMMON_PHY_CFG, &mut link).await.ok();
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link[0] & 1 == 1
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}
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}
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