mirror of
https://github.com/embassy-rs/embassy.git
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2569d38ab4
Move common bits up to spi/mod.rs. Isolate the RNG interrupt in a sub-module to avoid conflict with the const.
253 lines
9.0 KiB
Python
253 lines
9.0 KiB
Python
import xmltodict
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import yaml
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import re
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import json
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import os
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import toml
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from collections import OrderedDict
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from glob import glob
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abspath = os.path.abspath(__file__)
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dname = os.path.dirname(abspath)
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os.chdir(dname)
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# ======= load chips
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chips = {}
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for f in sorted(glob('stm32-data/data/chips/*.yaml')):
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if 'STM32F4' not in f and 'STM32L4' not in f:
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continue
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with open(f, 'r') as f:
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chip = yaml.load(f, Loader=yaml.CSafeLoader)
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chip['name'] = chip['name'].lower()
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chip['features'] = set()
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family = chip["family"].lower().replace('+', 'p')
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chip['features'].add(f'_{family}')
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print(chip['name'])
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chips[chip['name']] = chip
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# ======= load GPIO AF
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gpio_afs = {}
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for f in sorted(glob('stm32-data/data/gpio_af/*.yaml')):
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name = f.split('/')[-1].split('.')[0]
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with open(f, 'r') as f:
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af = yaml.load(f, Loader=yaml.CSafeLoader)
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gpio_afs[name] = af
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# ========= Generate pac/mod.rs
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with open('src/pac/mod.rs', 'w') as f:
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for chip in chips.values():
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f.write(
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f'#[cfg_attr(feature="{chip["name"]}", path="{chip["name"]}.rs")]\n')
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f.write('mod chip;\n')
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f.write('pub use chip::*;\n')
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# ========= Generate pac/stm32xxx.rs
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for chip in chips.values():
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print(f'generating {chip["name"]}')
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with open(f'src/pac/{chip["name"]}.rs', 'w') as f:
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f.write("""
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#![allow(dead_code)]
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#![allow(unused_imports)]
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#![allow(non_snake_case)]
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""")
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af = gpio_afs[chip['gpio_af']]
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peripheral_names = [] # USART1, PA5, EXTI8
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peripheral_versions = {} # usart -> v1, syscfg -> f4
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pins = set() # set of all present pins. PA4, PA5...
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# TODO this should probably come from the yamls?
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# We don't want to hardcode the EXTI peripheral addr
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gpio_base = chip['peripherals']['GPIOA']['address']
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gpio_stride = 0x400
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f.write(f"""
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pub fn GPIO(n: usize) -> gpio::Gpio {{
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gpio::Gpio((0x{gpio_base:x} + 0x{gpio_stride:x}*n) as _)
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}}
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""")
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# ========= peripherals
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peripheral_names.extend((f'EXTI{x}' for x in range(16)))
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for (name, peri) in chip['peripherals'].items():
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if 'block' not in peri:
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continue
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block = peri['block']
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block_mod, block_name = block.rsplit('/')
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block_mod, block_version = block_mod.rsplit('_')
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block_name = block_name.capitalize()
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# Check all peripherals have the same version: it's not OK for the same chip to use both usart_v1 and usart_v2
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if old_version := peripheral_versions.get(block_mod):
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if old_version != block_version:
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raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}')
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peripheral_versions[block_mod] = block_version
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# Set features
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chip['features'].add(f'_{block_mod}')
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chip['features'].add(f'_{block_mod}_{block_version}')
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f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);')
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custom_singletons = False
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if block_mod == 'usart':
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f.write(f'impl_usart!({name});')
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for pin, funcs in af.items():
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if pin in pins:
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if func := funcs.get(f'{name}_RX'):
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f.write(f'impl_usart_pin!({name}, RxPin, {pin}, {func});')
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if func := funcs.get(f'{name}_TX'):
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f.write(f'impl_usart_pin!({name}, TxPin, {pin}, {func});')
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if func := funcs.get(f'{name}_CTS'):
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f.write(f'impl_usart_pin!({name}, CtsPin, {pin}, {func});')
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if func := funcs.get(f'{name}_RTS'):
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f.write(f'impl_usart_pin!({name}, RtsPin, {pin}, {func});')
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if func := funcs.get(f'{name}_CK'):
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f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});')
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if block_mod == 'rng':
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if 'RNG' in chip['interrupts']:
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f.write(f'impl_rng!({name}, RNG);')
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else:
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f.write(f'impl_rng!({name}, HASH_RNG);')
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if block_mod == 'spi':
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clock = peri['clock']
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f.write(f'impl_spi!({name}, {clock});')
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for pin, funcs in af.items():
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if pin in pins:
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if func := funcs.get(f'{name}_SCK'):
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f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});')
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if func := funcs.get(f'{name}_MOSI'):
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f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});')
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if func := funcs.get(f'{name}_MISO'):
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f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});')
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if block_mod == 'gpio':
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custom_singletons = True
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port = name[4:]
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port_num = ord(port) - ord('A')
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assert peri['address'] == gpio_base + gpio_stride*port_num
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for pin_num in range(16):
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pin = f'P{port}{pin_num}'
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pins.add(pin)
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peripheral_names.append(pin)
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f.write(f'impl_gpio_pin!({pin}, {port_num}, {pin_num}, EXTI{pin_num});')
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if block_mod == 'dma':
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custom_singletons = True
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for ch_num in range(8):
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channel = f'{name}_CH{ch_num}'
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peripheral_names.append(channel)
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f.write(f'impl_dma_channel!({channel}, {name}, {ch_num});')
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if not custom_singletons:
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peripheral_names.append(name)
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for mod, version in peripheral_versions.items():
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f.write(f'pub use regs::{mod}_{version} as {mod};')
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f.write(f"""
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mod regs;
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pub use regs::generic;
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use embassy_extras::peripherals;
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peripherals!({','.join(peripheral_names)});
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""")
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# ========= interrupts
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irq_variants = []
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irq_vectors = []
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irq_fns = []
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irq_declares = []
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irqs = {num: name for name, num in chip['interrupts'].items()}
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irq_count = max(irqs.keys()) + 1
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for num, name in irqs.items():
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irq_variants.append(f'{name} = {num},')
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irq_fns.append(f'fn {name}();')
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irq_declares.append(f'declare!({name});')
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for num in range(irq_count):
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if name := irqs.get(num):
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irq_vectors.append(f'Vector {{ _handler: {name} }},')
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else:
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irq_vectors.append(f'Vector {{ _reserved: 0 }},')
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f.write(f"""
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pub mod interrupt {{
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pub use cortex_m::interrupt::{{CriticalSection, Mutex}};
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pub use embassy::interrupt::{{declare, take, Interrupt}};
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pub use embassy_extras::interrupt::Priority4 as Priority;
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[allow(non_camel_case_types)]
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enum InterruptEnum {{
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{''.join(irq_variants)}
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}}
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unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {{
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#[inline(always)]
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fn number(self) -> u16 {{
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self as u16
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}}
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}}
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{''.join(irq_declares)}
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}}
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mod interrupt_vector {{
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extern "C" {{
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{''.join(irq_fns)}
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}}
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pub union Vector {{
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_handler: unsafe extern "C" fn(),
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_reserved: u32,
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}}
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#[link_section = ".vector_table.interrupts"]
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#[no_mangle]
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pub static __INTERRUPTS: [Vector; {irq_count}] = [
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{''.join(irq_vectors)}
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];
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}}
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""")
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# ========= Update Cargo features
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feature_optional_deps = {}
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feature_optional_deps['_rng'] = ['rand_core']
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features = {}
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extra_features = set()
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for name, chip in chips.items():
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features[name] = sorted(list(chip['features']))
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for feature in chip['features']:
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extra_features.add(feature)
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for feature in sorted(list(extra_features)):
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features[feature] = feature_optional_deps.get(feature) or []
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SEPARATOR_START = '# BEGIN GENERATED FEATURES\n'
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SEPARATOR_END = '# END GENERATED FEATURES\n'
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with open('Cargo.toml', 'r') as f:
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cargo = f.read()
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before, cargo = cargo.split(SEPARATOR_START, maxsplit=1)
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_, after = cargo.split(SEPARATOR_END, maxsplit=1)
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cargo = before + SEPARATOR_START + toml.dumps(features) + SEPARATOR_END + after
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with open('Cargo.toml', 'w') as f:
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f.write(cargo)
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# ========= Generate pac/regs.rs
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os.system('cargo run --manifest-path ../../svd2rust/Cargo.toml -- generate --dir stm32-data/data/registers')
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os.system('mv lib.rs src/pac/regs.rs')
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# ========= Update Cargo features
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os.system('rustfmt src/pac/*')
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