14 Commits

Author	SHA1	Message	Date
Ulf Lilleengen	459049d604	Workaround for L4	2021-06-08 17:20:29 +02:00
Ulf Lilleengen	ee47a3e802	Add workaround for STM32H7	2021-06-08 17:20:29 +02:00
Ulf Lilleengen	ee3b82b743	Auto generate SPI v2 clock enable ... Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral. Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.	2021-06-08 17:20:29 +02:00
Dario Nieuwenhuis	b65c3c7160	stm32-metapac: Do not generate cfgs metadata	2021-06-07 05:13:30 +02:00
Dario Nieuwenhuis	3be49d3e79	fmt: Add dunmy use to avoid "unused variable" errors when no log is enabled.	2021-06-07 03:21:37 +02:00
Bob McWhirter	d75bf143eb	Remove the exti_interrupts table.	2021-06-03 14:18:58 -04:00
Bob McWhirter	fe47f781be	Migrate exti_irq stuff to macro tables.	2021-06-03 13:35:27 -04:00
Bob McWhirter	6958091b50	Move DAC, I2C, SPI and RNG to macro-tables.	2021-06-03 13:12:38 -04:00
Bob McWhirter	d4d914ea50	Remove the Option around the pins Vec.	2021-06-03 13:12:38 -04:00
Bob McWhirter	be180c1c52	Create the new peripheral_pins! macro table.	2021-06-03 13:12:38 -04:00
Dario Nieuwenhuis	2aa836b068	Fix L4+ family cfg	2021-06-01 15:57:25 +02:00
Dario Nieuwenhuis	1f2097ab11	cortex-m-rt is not a build dep	2021-06-01 15:53:44 +02:00
Dario Nieuwenhuis	60f12c78dd	Add resolver=2	2021-05-31 02:43:59 +02:00
Dario Nieuwenhuis	d8e4421fc6	Add stm32-metapac crate, with codegen in rust	2021-05-31 02:40:58 +02:00