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Add support for setting up the nRFs internal DCDCs
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deadf40c85
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@ -184,6 +184,34 @@ pub mod config {
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NotConfigured,
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NotConfigured,
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}
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}
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/// Settings for enabling the built in DCDC converters.
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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pub struct DcdcConfig {
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/// Config for the first stage DCDC (VDDH -> VDD), if disabled LDO will be used.
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#[cfg(feature = "nrf52840")]
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pub reg0: bool,
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/// Config for the second stage DCDC (VDD -> DEC4), if disabled LDO will be used.
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pub reg1: bool,
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}
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/// Settings for enabling the built in DCDC converters.
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#[cfg(feature = "_nrf5340-app")]
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pub struct DcdcConfig {
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/// Config for the high voltage stage, if disabled LDO will be used.
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pub regh: bool,
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/// Config for the main rail, if disabled LDO will be used.
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pub regmain: bool,
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/// Config for the radio rail, if disabled LDO will be used.
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pub regradio: bool,
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}
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/// Settings for enabling the built in DCDC converter.
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#[cfg(feature = "_nrf9160")]
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pub struct DcdcConfig {
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/// Config for the main rail, if disabled LDO will be used.
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pub regmain: bool,
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}
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/// Configuration for peripherals. Default configuration should work on any nRF chip.
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/// Configuration for peripherals. Default configuration should work on any nRF chip.
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#[non_exhaustive]
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#[non_exhaustive]
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pub struct Config {
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pub struct Config {
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@ -191,6 +219,9 @@ pub mod config {
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pub hfclk_source: HfclkSource,
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pub hfclk_source: HfclkSource,
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/// Low frequency clock source.
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/// Low frequency clock source.
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pub lfclk_source: LfclkSource,
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pub lfclk_source: LfclkSource,
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#[cfg(not(feature = "_nrf5340-net"))]
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/// DCDC configuration.
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pub dcdc: DcdcConfig,
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/// GPIOTE interrupt priority. Should be lower priority than softdevice if used.
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/// GPIOTE interrupt priority. Should be lower priority than softdevice if used.
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#[cfg(feature = "gpiote")]
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#[cfg(feature = "gpiote")]
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pub gpiote_interrupt_priority: crate::interrupt::Priority,
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pub gpiote_interrupt_priority: crate::interrupt::Priority,
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@ -209,6 +240,20 @@ pub mod config {
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// xtals if they know they have them.
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// xtals if they know they have them.
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hfclk_source: HfclkSource::Internal,
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hfclk_source: HfclkSource::Internal,
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lfclk_source: LfclkSource::InternalRC,
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lfclk_source: LfclkSource::InternalRC,
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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dcdc: DcdcConfig {
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#[cfg(feature = "nrf52840")]
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reg0: false,
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reg1: false,
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},
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#[cfg(feature = "_nrf5340-app")]
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dcdc: DcdcConfig {
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regh: false,
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regmain: false,
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regradio: false,
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},
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#[cfg(feature = "_nrf9160")]
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dcdc: DcdcConfig { regmain: false },
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#[cfg(feature = "gpiote")]
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#[cfg(feature = "gpiote")]
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gpiote_interrupt_priority: crate::interrupt::Priority::P0,
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gpiote_interrupt_priority: crate::interrupt::Priority::P0,
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#[cfg(feature = "_time-driver")]
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#[cfg(feature = "_time-driver")]
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@ -454,6 +499,41 @@ pub fn init(config: config::Config) -> Peripherals {
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r.tasks_lfclkstart.write(|w| unsafe { w.bits(1) });
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r.tasks_lfclkstart.write(|w| unsafe { w.bits(1) });
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while r.events_lfclkstarted.read().bits() == 0 {}
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while r.events_lfclkstarted.read().bits() == 0 {}
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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{
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// Setup DCDCs.
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let pwr = unsafe { &*pac::POWER::ptr() };
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#[cfg(feature = "nrf52840")]
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if config.dcdc.reg0 {
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pwr.dcdcen0.write(|w| w.dcdcen().set_bit());
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}
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if config.dcdc.reg1 {
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pwr.dcdcen.write(|w| w.dcdcen().set_bit());
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}
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}
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#[cfg(feature = "_nrf9160")]
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{
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// Setup DCDC.
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let reg = unsafe { &*pac::REGULATORS::ptr() };
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if config.dcdc.regmain {
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reg.dcdcen.write(|w| w.dcdcen().set_bit());
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}
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}
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#[cfg(feature = "_nrf5340-app")]
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{
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// Setup DCDC.
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let reg = unsafe { &*pac::REGULATORS::ptr() };
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if config.dcdc.regh {
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reg.vregh.dcdcen.write(|w| w.dcdcen().set_bit());
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}
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if config.dcdc.regmain {
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reg.vregmain.dcdcen.write(|w| w.dcdcen().set_bit());
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}
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if config.dcdc.regradio {
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reg.vregradio.dcdcen.write(|w| w.dcdcen().set_bit());
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}
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}
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// Init GPIOTE
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// Init GPIOTE
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#[cfg(feature = "gpiote")]
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#[cfg(feature = "gpiote")]
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gpiote::init(config.gpiote_interrupt_priority);
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gpiote::init(config.gpiote_interrupt_priority);
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