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Change atomics and add a fence.
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cf5b7dc943
commit
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@ -74,7 +74,7 @@ pub(crate) async unsafe fn transfer_p2m(
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let res = poll_fn(|cx| {
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STATE.ch_wakers[n].register(cx.waker());
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match STATE.ch_status[n].load(Ordering::Relaxed) {
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match STATE.ch_status[n].load(Ordering::Acquire) {
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CH_STATUS_NONE => Poll::Pending,
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x => Poll::Ready(x),
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}
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@ -105,6 +105,7 @@ pub(crate) async unsafe fn transfer_m2p(
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c.par().write_value(dst as _);
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c.m0ar().write_value(src.as_ptr() as _);
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c.ndtr().write_value(regs::Ndtr(src.len() as _));
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compiler_fence(Ordering::AcqRel);
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c.cr().write(|w| {
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w.set_dir(vals::Dir::MEMORYTOPERIPHERAL);
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w.set_msize(vals::Size::BITS8);
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@ -120,7 +121,7 @@ pub(crate) async unsafe fn transfer_m2p(
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let res = poll_fn(|cx| {
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STATE.ch_wakers[n].register(cx.waker());
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match STATE.ch_status[n].load(Ordering::Relaxed) {
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match STATE.ch_status[n].load(Ordering::Acquire) {
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CH_STATUS_NONE => {
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let left = c.ndtr().read().ndt();
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Poll::Pending
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@ -130,6 +131,8 @@ pub(crate) async unsafe fn transfer_m2p(
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})
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.await;
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compiler_fence(Ordering::AcqRel);
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// TODO handle error
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assert!(res == CH_STATUS_COMPLETED);
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}
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@ -145,10 +148,10 @@ unsafe fn on_irq() {
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for chn in 0..4 {
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let n = dman * 8 + isrn * 4 + chn;
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if isr.teif(chn) {
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STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
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STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Release);
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STATE.ch_wakers[n].wake();
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} else if isr.tcif(chn) {
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STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
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STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Release);
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STATE.ch_wakers[n].wake();
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}
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}
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@ -298,6 +301,7 @@ pub struct M2P;
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#[cfg(usart)]
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use crate::usart;
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use atomic_polyfill::compiler_fence;
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peripheral_dma_channels! {
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($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
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impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
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