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Add feature gate for f7
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@ -1,11 +1,12 @@
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//! DSI HOST
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use crate::rcc::RccPeripheral;
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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//use crate::gpio::{AnyPin, SealedPin};
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use crate::gpio::{AFType, AnyPin, Pull, Speed};
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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/// Performs a busy-wait delay for a specified number of microseconds.
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@ -1,7 +1,8 @@
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//! LTDC
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use core::marker::PhantomData;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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use core::marker::PhantomData;
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/// LTDC driver.
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pub struct Ltdc<'d, T: Instance> {
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@ -47,6 +48,12 @@ impl<'d, T: Instance> Ltdc<'d, T> {
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critical_section::with(|_cs| {
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// RM says the pllsaidivr should only be changed when pllsai is off. But this could have other unintended side effects. So let's just give it a try like this.
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// According to the debugger, this bit gets set, anyway.
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#[cfg(stm32f7)]
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stm32_metapac::RCC
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.dckcfgr1()
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.modify(|w| w.set_pllsaidivr(stm32_metapac::rcc::vals::Pllsaidivr::DIV2));
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#[cfg(not(stm32f7))]
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stm32_metapac::RCC
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.dckcfgr()
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.modify(|w| w.set_pllsaidivr(stm32_metapac::rcc::vals::Pllsaidivr::DIV2));
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