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stm32/rcc: refactor and unify f4 into f7.
This commit is contained in:
parent
67010d123c
commit
f20f170b1f
@ -58,7 +58,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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critical-section = "1.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6f7449303bf8af60a63704d35df9af46006c6148" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526" }
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vcell = "0.1.3"
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vcell = "0.1.3"
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bxcan = "0.7.0"
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bxcan = "0.7.0"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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[build-dependencies]
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proc-macro2 = "1.0.36"
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6f7449303bf8af60a63704d35df9af46006c6148", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526", default-features = false, features = ["metadata"]}
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[features]
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[features]
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@ -1,400 +0,0 @@
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use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllq, Pllr, Ppre, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// Clocks configuration
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub hclk: Option<Hertz>,
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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pub plli2s: Option<Hertz>,
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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pub pllsai: Option<Hertz>,
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pub pll48: bool,
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pub ls: super::LsConfig,
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}
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#[cfg(stm32f410)]
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fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
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None
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}
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// Not currently implemented, but will be in the future
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#[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
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fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
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None
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}
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423)))]
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fn calculate_sai_i2s_pll_values(vco_in: u32, max_div: u32, target: Option<u32>) -> Option<(u32, u32, u32)> {
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let min_div = 2;
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let target = match target {
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Some(target) => target,
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None => return None,
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};
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// We loop through the possible divider values to find the best configuration. Looping
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// through all possible "N" values would result in more iterations.
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let (n, outdiv, output, _error) = (min_div..=max_div)
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.filter_map(|outdiv| {
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let target_vco_out = match target.checked_mul(outdiv) {
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Some(x) => x,
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None => return None,
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};
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let n = (target_vco_out + (vco_in >> 1)) / vco_in;
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let vco_out = vco_in * n;
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if !(100_000_000..=432_000_000).contains(&vco_out) {
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return None;
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}
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let output = vco_out / outdiv;
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let error = (output as i32 - target as i32).unsigned_abs();
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Some((n, outdiv, output, error))
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})
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.min_by_key(|(_, _, _, error)| *error)?;
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Some((n, outdiv, output))
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}
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
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let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 7, plli2s)?;
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RCC.plli2scfgr().modify(|w| {
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w.set_plli2sn(n as u16);
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w.set_plli2sr(outdiv as u8);
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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w.set_plli2sq(outdiv as u8); //set sai divider same as i2s
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});
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Some(output)
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}
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#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
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fn setup_sai_pll(_vco_in: u32, _pllsai: Option<u32>) -> Option<u32> {
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None
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}
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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fn setup_sai_pll(vco_in: u32, pllsai: Option<u32>) -> Option<u32> {
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let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 15, pllsai)?;
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RCC.pllsaicfgr().modify(|w| {
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w.set_pllsain(n as u16);
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w.set_pllsaiq(outdiv as u8);
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});
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Some(output)
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}
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fn setup_pll(
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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plli2s: Option<u32>,
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pllsai: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
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return PllResults {
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use_pll: false,
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pllsysclk: None,
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pll48clk: None,
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plli2sclk: None,
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pllsaiclk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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// the range from 1 to 2 MHz
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let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
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let pllm_max = pllsrcclk / 1_000_000;
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
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let vco_in = pllsrcclk / pllm;
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let plln = target_freq / vco_in;
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target_freq - vco_in * plln
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}));
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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let plln = if pll48clk {
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// try the different valid pllq according to the valid
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// main scaller values, and take the best
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let pllq = unwrap!((4..=9).min_by_key(|pllq| {
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let plln = 48_000_000 * pllq / vco_in;
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let pll48_diff = 48_000_000 - vco_in * plln / pllq;
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let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
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(pll48_diff, sysclk_diff)
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}));
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48_000_000 * pllq / vco_in
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} else {
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sysclk * sysclk_div / vco_in
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};
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let pllp = (sysclk_div / 2) - 1;
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let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
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let real_pll48clk = vco_in * plln / pllq;
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RCC.pllcfgr().modify(|w| {
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w.set_pllm(Pllm::from_bits(pllm as u8));
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w.set_plln(Plln::from_bits(plln as u16));
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w.set_pllp(Pllp::from_bits(pllp as u8));
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w.set_pllq(Pllq::from_bits(pllq as u8));
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w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
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w.set_pllr(Pllr::from_bits(0));
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});
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let real_pllsysclk = vco_in * plln / sysclk_div;
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PllResults {
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use_pll: true,
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pllsysclk: Some(real_pllsysclk),
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pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
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plli2sclk: setup_i2s_pll(vco_in, plli2s),
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pllsaiclk: setup_sai_pll(vco_in, pllsai),
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}
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}
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fn flash_setup(sysclk: u32) {
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use crate::pac::flash::vals::Latency;
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// Be conservative with voltage ranges
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const FLASH_LATENCY_STEP: u32 = 30_000_000;
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critical_section::with(|_| {
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FLASH
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.acr()
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.modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
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});
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}
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pub(crate) unsafe fn init(config: Config) {
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let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
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let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let sysclk_on_pll = sysclk != pllsrcclk;
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let plls = setup_pll(
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pllsrcclk,
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config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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config.plli2s.map(|i2s| i2s.0),
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
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None,
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
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config.pllsai.map(|sai| sai.0),
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#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
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None,
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config.pll48,
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);
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if config.pll48 {
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let freq = unwrap!(plls.pll48clk);
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assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
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}
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let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
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// AHB prescaler
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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let pclk1 = config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= max::PCLK1_MAX);
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let pclk2 = config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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// Calculate real APB2 clock
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= max::PCLK2_MAX);
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flash_setup(sysclk);
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if config.hse.is_some() {
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RCC.cr().modify(|w| {
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w.set_hsebyp(config.bypass_hse);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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if plls.use_pll {
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RCC.cr().modify(|w| w.set_pllon(true));
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if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
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|
||||||
PWR.cr1().modify(|w| w.set_oden(true));
|
|
||||||
while !PWR.csr1().read().odrdy() {}
|
|
||||||
|
|
||||||
PWR.cr1().modify(|w| w.set_odswen(true));
|
|
||||||
while !PWR.csr1().read().odswrdy() {}
|
|
||||||
}
|
|
||||||
|
|
||||||
while !RCC.cr().read().pllrdy() {}
|
|
||||||
}
|
|
||||||
|
|
||||||
#[cfg(not(stm32f410))]
|
|
||||||
if plls.plli2sclk.is_some() {
|
|
||||||
RCC.cr().modify(|w| w.set_plli2son(true));
|
|
||||||
|
|
||||||
while !RCC.cr().read().plli2srdy() {}
|
|
||||||
}
|
|
||||||
|
|
||||||
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
|
|
||||||
if plls.pllsaiclk.is_some() {
|
|
||||||
RCC.cr().modify(|w| w.set_pllsaion(true));
|
|
||||||
while !RCC.cr().read().pllsairdy() {}
|
|
||||||
}
|
|
||||||
|
|
||||||
RCC.cfgr().modify(|w| {
|
|
||||||
w.set_ppre2(Ppre::from_bits(ppre2_bits));
|
|
||||||
w.set_ppre1(Ppre::from_bits(ppre1_bits));
|
|
||||||
w.set_hpre(hpre_bits);
|
|
||||||
});
|
|
||||||
|
|
||||||
// Wait for the new prescalers to kick in
|
|
||||||
// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
|
|
||||||
cortex_m::asm::delay(16);
|
|
||||||
|
|
||||||
RCC.cfgr().modify(|w| {
|
|
||||||
w.set_sw(if sysclk_on_pll {
|
|
||||||
Sw::PLL1_P
|
|
||||||
} else if config.hse.is_some() {
|
|
||||||
Sw::HSE
|
|
||||||
} else {
|
|
||||||
Sw::HSI
|
|
||||||
})
|
|
||||||
});
|
|
||||||
|
|
||||||
let rtc = config.ls.init();
|
|
||||||
|
|
||||||
set_freqs(Clocks {
|
|
||||||
sys: Hertz(sysclk),
|
|
||||||
pclk1: Hertz(pclk1),
|
|
||||||
pclk2: Hertz(pclk2),
|
|
||||||
|
|
||||||
pclk1_tim: Hertz(pclk1 * timer_mul1),
|
|
||||||
pclk2_tim: Hertz(pclk2 * timer_mul2),
|
|
||||||
|
|
||||||
hclk1: Hertz(hclk),
|
|
||||||
hclk2: Hertz(hclk),
|
|
||||||
hclk3: Hertz(hclk),
|
|
||||||
|
|
||||||
pll1_q: plls.pll48clk.map(Hertz),
|
|
||||||
|
|
||||||
#[cfg(not(stm32f410))]
|
|
||||||
plli2s1_q: plls.plli2sclk.map(Hertz),
|
|
||||||
#[cfg(not(stm32f410))]
|
|
||||||
plli2s1_r: None,
|
|
||||||
|
|
||||||
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
|
|
||||||
pllsai1_q: plls.pllsaiclk.map(Hertz),
|
|
||||||
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
|
|
||||||
pllsai1_r: None,
|
|
||||||
|
|
||||||
rtc,
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
struct PllResults {
|
|
||||||
use_pll: bool,
|
|
||||||
pllsysclk: Option<u32>,
|
|
||||||
pll48clk: Option<u32>,
|
|
||||||
#[allow(dead_code)]
|
|
||||||
plli2sclk: Option<u32>,
|
|
||||||
#[allow(dead_code)]
|
|
||||||
pllsaiclk: Option<u32>,
|
|
||||||
}
|
|
||||||
|
|
||||||
mod max {
|
|
||||||
#[cfg(stm32f401)]
|
|
||||||
pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
|
|
||||||
#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
|
|
||||||
pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
|
|
||||||
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
|
|
||||||
pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
|
|
||||||
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
|
|
||||||
pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
|
|
||||||
|
|
||||||
pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;
|
|
||||||
|
|
||||||
pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
|
|
||||||
|
|
||||||
#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
|
|
||||||
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
|
|
||||||
#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
|
|
||||||
pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
|
|
||||||
|
|
||||||
pub(crate) const PLL_48_CLK: u32 = 48_000_000;
|
|
||||||
pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
|
|
||||||
}
|
|
@ -6,6 +6,20 @@ use crate::pac::{FLASH, PWR, RCC};
|
|||||||
use crate::rcc::{set_freqs, Clocks};
|
use crate::rcc::{set_freqs, Clocks};
|
||||||
use crate::time::Hertz;
|
use crate::time::Hertz;
|
||||||
|
|
||||||
|
// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
|
||||||
|
// TODO: on some F4s, add support for plli2s_src
|
||||||
|
//
|
||||||
|
// plli2s plli2s_m plli2s_src pllsai pllsai_m
|
||||||
|
// f401 y shared
|
||||||
|
// f410
|
||||||
|
// f411 y individual
|
||||||
|
// f412 y individual y
|
||||||
|
// f4[12]3 y individual y
|
||||||
|
// f446 y individual y individual
|
||||||
|
// f4[67]9 y shared y shared
|
||||||
|
// f4[23][79] y shared y shared
|
||||||
|
// f4[01][57] y shared
|
||||||
|
|
||||||
/// HSI speed
|
/// HSI speed
|
||||||
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
|
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
|
||||||
|
|
||||||
@ -51,7 +65,9 @@ pub struct Config {
|
|||||||
pub pll_src: PllSource,
|
pub pll_src: PllSource,
|
||||||
|
|
||||||
pub pll: Option<Pll>,
|
pub pll: Option<Pll>,
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
pub plli2s: Option<Pll>,
|
pub plli2s: Option<Pll>,
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
pub pllsai: Option<Pll>,
|
pub pllsai: Option<Pll>,
|
||||||
|
|
||||||
pub ahb_pre: AHBPrescaler,
|
pub ahb_pre: AHBPrescaler,
|
||||||
@ -69,7 +85,9 @@ impl Default for Config {
|
|||||||
sys: Sysclk::HSI,
|
sys: Sysclk::HSI,
|
||||||
pll_src: PllSource::HSI,
|
pll_src: PllSource::HSI,
|
||||||
pll: None,
|
pll: None,
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
plli2s: None,
|
plli2s: None,
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
pllsai: None,
|
pllsai: None,
|
||||||
|
|
||||||
ahb_pre: AHBPrescaler::DIV1,
|
ahb_pre: AHBPrescaler::DIV1,
|
||||||
@ -128,7 +146,9 @@ pub(crate) unsafe fn init(config: Config) {
|
|||||||
source: config.pll_src,
|
source: config.pll_src,
|
||||||
};
|
};
|
||||||
let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
|
let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
|
let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
|
let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
|
||||||
|
|
||||||
// Configure sysclk
|
// Configure sysclk
|
||||||
@ -171,6 +191,15 @@ pub(crate) unsafe fn init(config: Config) {
|
|||||||
pclk2_tim,
|
pclk2_tim,
|
||||||
rtc,
|
rtc,
|
||||||
pll1_q: pll.q,
|
pll1_q: pll.q,
|
||||||
|
#[cfg(all(rcc_f4, not(stm32f410)))]
|
||||||
|
plli2s1_q: _plli2s.q,
|
||||||
|
#[cfg(all(rcc_f4, not(stm32f410)))]
|
||||||
|
plli2s1_r: _plli2s.r,
|
||||||
|
|
||||||
|
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
|
||||||
|
pllsai1_q: _pllsai.q,
|
||||||
|
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
|
||||||
|
pllsai1_r: _pllsai.r,
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -191,7 +220,9 @@ struct PllOutput {
|
|||||||
#[derive(PartialEq, Eq, Clone, Copy)]
|
#[derive(PartialEq, Eq, Clone, Copy)]
|
||||||
enum PllInstance {
|
enum PllInstance {
|
||||||
Pll,
|
Pll,
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
Plli2s,
|
Plli2s,
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
Pllsai,
|
Pllsai,
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -201,10 +232,12 @@ fn pll_enable(instance: PllInstance, enabled: bool) {
|
|||||||
RCC.cr().modify(|w| w.set_pllon(enabled));
|
RCC.cr().modify(|w| w.set_pllon(enabled));
|
||||||
while RCC.cr().read().pllrdy() != enabled {}
|
while RCC.cr().read().pllrdy() != enabled {}
|
||||||
}
|
}
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
PllInstance::Plli2s => {
|
PllInstance::Plli2s => {
|
||||||
RCC.cr().modify(|w| w.set_plli2son(enabled));
|
RCC.cr().modify(|w| w.set_plli2son(enabled));
|
||||||
while RCC.cr().read().plli2srdy() != enabled {}
|
while RCC.cr().read().plli2srdy() != enabled {}
|
||||||
}
|
}
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
PllInstance::Pllsai => {
|
PllInstance::Pllsai => {
|
||||||
RCC.cr().modify(|w| w.set_pllsaion(enabled));
|
RCC.cr().modify(|w| w.set_pllsaion(enabled));
|
||||||
while RCC.cr().read().pllsairdy() != enabled {}
|
while RCC.cr().read().pllsairdy() != enabled {}
|
||||||
@ -255,9 +288,11 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
|
|||||||
w.set_pllsrc(input.source);
|
w.set_pllsrc(input.source);
|
||||||
write_fields!(w);
|
write_fields!(w);
|
||||||
}),
|
}),
|
||||||
|
#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
|
||||||
PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
|
PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
|
||||||
write_fields!(w);
|
write_fields!(w);
|
||||||
}),
|
}),
|
||||||
|
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
|
||||||
PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
|
PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
|
||||||
write_fields!(w);
|
write_fields!(w);
|
||||||
}),
|
}),
|
||||||
@ -294,6 +329,7 @@ where
|
|||||||
(pclk, pclk_tim)
|
(pclk, pclk_tim)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[cfg(stm32f7)]
|
||||||
mod max {
|
mod max {
|
||||||
use core::ops::RangeInclusive;
|
use core::ops::RangeInclusive;
|
||||||
|
|
||||||
@ -310,3 +346,34 @@ mod max {
|
|||||||
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
|
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
|
||||||
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
|
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[cfg(stm32f4)]
|
||||||
|
mod max {
|
||||||
|
use core::ops::RangeInclusive;
|
||||||
|
|
||||||
|
use crate::time::Hertz;
|
||||||
|
|
||||||
|
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
|
||||||
|
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
|
||||||
|
|
||||||
|
#[cfg(stm32f401)]
|
||||||
|
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(84_000_000);
|
||||||
|
#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
|
||||||
|
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(168_000_000);
|
||||||
|
#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
|
||||||
|
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(100_000_000);
|
||||||
|
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
|
||||||
|
pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(180_000_000);
|
||||||
|
|
||||||
|
pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
|
||||||
|
|
||||||
|
pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(PCLK2.end().0 / 2);
|
||||||
|
|
||||||
|
#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
|
||||||
|
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0);
|
||||||
|
#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
|
||||||
|
pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0 / 2);
|
||||||
|
|
||||||
|
pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
|
||||||
|
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
|
||||||
|
}
|
@ -13,8 +13,7 @@ pub use mco::*;
|
|||||||
#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
|
#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
|
||||||
#[cfg_attr(rcc_f2, path = "f2.rs")]
|
#[cfg_attr(rcc_f2, path = "f2.rs")]
|
||||||
#[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
|
#[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
|
||||||
#[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
|
#[cfg_attr(any(rcc_f4, rcc_f410, rcc_f7), path = "f4f7.rs")]
|
||||||
#[cfg_attr(rcc_f7, path = "f7.rs")]
|
|
||||||
#[cfg_attr(rcc_c0, path = "c0.rs")]
|
#[cfg_attr(rcc_c0, path = "c0.rs")]
|
||||||
#[cfg_attr(rcc_g0, path = "g0.rs")]
|
#[cfg_attr(rcc_g0, path = "g0.rs")]
|
||||||
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
||||||
|
@ -10,7 +10,7 @@ use embassy_stm32::eth::generic_smi::GenericSMI;
|
|||||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||||
use embassy_stm32::peripherals::ETH;
|
use embassy_stm32::peripherals::ETH;
|
||||||
use embassy_stm32::rng::Rng;
|
use embassy_stm32::rng::Rng;
|
||||||
use embassy_stm32::time::mhz;
|
use embassy_stm32::time::Hertz;
|
||||||
use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
|
use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
|
||||||
use embassy_time::Timer;
|
use embassy_time::Timer;
|
||||||
use embedded_io_async::Write;
|
use embedded_io_async::Write;
|
||||||
@ -32,7 +32,25 @@ async fn net_task(stack: &'static Stack<Device>) -> ! {
|
|||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
async fn main(spawner: Spawner) -> ! {
|
async fn main(spawner: Spawner) -> ! {
|
||||||
let mut config = Config::default();
|
let mut config = Config::default();
|
||||||
config.rcc.sys_ck = Some(mhz(200));
|
{
|
||||||
|
use embassy_stm32::rcc::*;
|
||||||
|
config.rcc.hse = Some(Hse {
|
||||||
|
freq: Hertz(8_000_000),
|
||||||
|
mode: HseMode::Bypass,
|
||||||
|
});
|
||||||
|
config.rcc.pll_src = PllSource::HSE;
|
||||||
|
config.rcc.pll = Some(Pll {
|
||||||
|
prediv: PllPreDiv::DIV4,
|
||||||
|
mul: PllMul::MUL180,
|
||||||
|
divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
|
||||||
|
divq: None,
|
||||||
|
divr: None,
|
||||||
|
});
|
||||||
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||||
|
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||||
|
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||||
|
config.rcc.sys = Sysclk::PLL1_P;
|
||||||
|
}
|
||||||
let p = embassy_stm32::init(config);
|
let p = embassy_stm32::init(config);
|
||||||
|
|
||||||
info!("Hello World!");
|
info!("Hello World!");
|
||||||
|
@ -4,15 +4,13 @@
|
|||||||
|
|
||||||
use defmt::info;
|
use defmt::info;
|
||||||
use embassy_executor::Spawner;
|
use embassy_executor::Spawner;
|
||||||
use embassy_stm32::time::Hertz;
|
|
||||||
use embassy_stm32::Config;
|
use embassy_stm32::Config;
|
||||||
use embassy_time::Timer;
|
use embassy_time::Timer;
|
||||||
use {defmt_rtt as _, panic_probe as _};
|
use {defmt_rtt as _, panic_probe as _};
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
async fn main(_spawner: Spawner) -> ! {
|
async fn main(_spawner: Spawner) -> ! {
|
||||||
let mut config = Config::default();
|
let config = Config::default();
|
||||||
config.rcc.sys_ck = Some(Hertz(84_000_000));
|
|
||||||
let _p = embassy_stm32::init(config);
|
let _p = embassy_stm32::init(config);
|
||||||
|
|
||||||
loop {
|
loop {
|
||||||
|
@ -5,7 +5,7 @@
|
|||||||
use defmt::*;
|
use defmt::*;
|
||||||
use embassy_executor::Spawner;
|
use embassy_executor::Spawner;
|
||||||
use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
|
use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
|
||||||
use embassy_stm32::time::mhz;
|
use embassy_stm32::time::{mhz, Hertz};
|
||||||
use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
|
use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
|
||||||
use {defmt_rtt as _, panic_probe as _};
|
use {defmt_rtt as _, panic_probe as _};
|
||||||
|
|
||||||
@ -20,8 +20,25 @@ bind_interrupts!(struct Irqs {
|
|||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
async fn main(_spawner: Spawner) {
|
async fn main(_spawner: Spawner) {
|
||||||
let mut config = Config::default();
|
let mut config = Config::default();
|
||||||
config.rcc.sys_ck = Some(mhz(48));
|
{
|
||||||
config.rcc.pll48 = true;
|
use embassy_stm32::rcc::*;
|
||||||
|
config.rcc.hse = Some(Hse {
|
||||||
|
freq: Hertz(8_000_000),
|
||||||
|
mode: HseMode::Bypass,
|
||||||
|
});
|
||||||
|
config.rcc.pll_src = PllSource::HSE;
|
||||||
|
config.rcc.pll = Some(Pll {
|
||||||
|
prediv: PllPreDiv::DIV4,
|
||||||
|
mul: PllMul::MUL168,
|
||||||
|
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
|
||||||
|
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
|
||||||
|
divr: None,
|
||||||
|
});
|
||||||
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||||
|
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||||
|
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||||
|
config.rcc.sys = Sysclk::PLL1_P;
|
||||||
|
}
|
||||||
let p = embassy_stm32::init(config);
|
let p = embassy_stm32::init(config);
|
||||||
info!("Hello World!");
|
info!("Hello World!");
|
||||||
|
|
||||||
|
@ -7,7 +7,7 @@ use embassy_executor::Spawner;
|
|||||||
use embassy_net::tcp::TcpSocket;
|
use embassy_net::tcp::TcpSocket;
|
||||||
use embassy_net::{Stack, StackResources};
|
use embassy_net::{Stack, StackResources};
|
||||||
use embassy_stm32::rng::{self, Rng};
|
use embassy_stm32::rng::{self, Rng};
|
||||||
use embassy_stm32::time::mhz;
|
use embassy_stm32::time::Hertz;
|
||||||
use embassy_stm32::usb_otg::Driver;
|
use embassy_stm32::usb_otg::Driver;
|
||||||
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
|
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
|
||||||
use embassy_usb::class::cdc_ncm::embassy_net::{Device, Runner, State as NetState};
|
use embassy_usb::class::cdc_ncm::embassy_net::{Device, Runner, State as NetState};
|
||||||
@ -46,9 +46,25 @@ async fn main(spawner: Spawner) {
|
|||||||
info!("Hello World!");
|
info!("Hello World!");
|
||||||
|
|
||||||
let mut config = Config::default();
|
let mut config = Config::default();
|
||||||
config.rcc.pll48 = true;
|
{
|
||||||
config.rcc.sys_ck = Some(mhz(48));
|
use embassy_stm32::rcc::*;
|
||||||
|
config.rcc.hse = Some(Hse {
|
||||||
|
freq: Hertz(8_000_000),
|
||||||
|
mode: HseMode::Bypass,
|
||||||
|
});
|
||||||
|
config.rcc.pll_src = PllSource::HSE;
|
||||||
|
config.rcc.pll = Some(Pll {
|
||||||
|
prediv: PllPreDiv::DIV4,
|
||||||
|
mul: PllMul::MUL168,
|
||||||
|
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
|
||||||
|
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
|
||||||
|
divr: None,
|
||||||
|
});
|
||||||
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||||
|
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||||
|
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||||
|
config.rcc.sys = Sysclk::PLL1_P;
|
||||||
|
}
|
||||||
let p = embassy_stm32::init(config);
|
let p = embassy_stm32::init(config);
|
||||||
|
|
||||||
// Create the driver, from the HAL.
|
// Create the driver, from the HAL.
|
||||||
|
@ -4,7 +4,7 @@
|
|||||||
|
|
||||||
use defmt::{panic, *};
|
use defmt::{panic, *};
|
||||||
use embassy_executor::Spawner;
|
use embassy_executor::Spawner;
|
||||||
use embassy_stm32::time::mhz;
|
use embassy_stm32::time::Hertz;
|
||||||
use embassy_stm32::usb_otg::{Driver, Instance};
|
use embassy_stm32::usb_otg::{Driver, Instance};
|
||||||
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
|
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
|
||||||
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
|
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
|
||||||
@ -22,9 +22,25 @@ async fn main(_spawner: Spawner) {
|
|||||||
info!("Hello World!");
|
info!("Hello World!");
|
||||||
|
|
||||||
let mut config = Config::default();
|
let mut config = Config::default();
|
||||||
config.rcc.pll48 = true;
|
{
|
||||||
config.rcc.sys_ck = Some(mhz(48));
|
use embassy_stm32::rcc::*;
|
||||||
|
config.rcc.hse = Some(Hse {
|
||||||
|
freq: Hertz(8_000_000),
|
||||||
|
mode: HseMode::Bypass,
|
||||||
|
});
|
||||||
|
config.rcc.pll_src = PllSource::HSE;
|
||||||
|
config.rcc.pll = Some(Pll {
|
||||||
|
prediv: PllPreDiv::DIV4,
|
||||||
|
mul: PllMul::MUL168,
|
||||||
|
divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
|
||||||
|
divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
|
||||||
|
divr: None,
|
||||||
|
});
|
||||||
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||||
|
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||||
|
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||||
|
config.rcc.sys = Sysclk::PLL1_P;
|
||||||
|
}
|
||||||
let p = embassy_stm32::init(config);
|
let p = embassy_stm32::init(config);
|
||||||
|
|
||||||
// Create the driver, from the HAL.
|
// Create the driver, from the HAL.
|
||||||
|
@ -224,11 +224,23 @@ pub fn config() -> Config {
|
|||||||
|
|
||||||
#[cfg(feature = "stm32f429zi")]
|
#[cfg(feature = "stm32f429zi")]
|
||||||
{
|
{
|
||||||
// TODO: stm32f429zi can do up to 180mhz, but that makes tests fail.
|
use embassy_stm32::rcc::*;
|
||||||
// perhaps we have some bug w.r.t overdrive.
|
config.rcc.hse = Some(Hse {
|
||||||
config.rcc.sys_ck = Some(Hertz(168_000_000));
|
freq: Hertz(8_000_000),
|
||||||
config.rcc.pclk1 = Some(Hertz(42_000_000));
|
mode: HseMode::Bypass,
|
||||||
config.rcc.pclk2 = Some(Hertz(84_000_000));
|
});
|
||||||
|
config.rcc.pll_src = PllSource::HSE;
|
||||||
|
config.rcc.pll = Some(Pll {
|
||||||
|
prediv: PllPreDiv::DIV4,
|
||||||
|
mul: PllMul::MUL180,
|
||||||
|
divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
|
||||||
|
divq: None,
|
||||||
|
divr: None,
|
||||||
|
});
|
||||||
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
||||||
|
config.rcc.apb1_pre = APBPrescaler::DIV4;
|
||||||
|
config.rcc.apb2_pre = APBPrescaler::DIV2;
|
||||||
|
config.rcc.sys = Sysclk::PLL1_P;
|
||||||
}
|
}
|
||||||
|
|
||||||
#[cfg(feature = "stm32f767zi")]
|
#[cfg(feature = "stm32f767zi")]
|
||||||
|
Loading…
Reference in New Issue
Block a user