nordic-dev.net/embassy
2
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2024-11-21 22:32:29 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1728 from pennae/rp-gpio-banks

Browse Source 
rp: fix qspi gpio interrupts, make qspi gpio optional
This commit is contained in:
Dario Nieuwenhuis 2023-08-01 08:18:39 +00:00 committed by GitHub
commit ef3b1f46a9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 84 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
ci.sh
View File

@ -58,6 +58,7 @@ cargo batch \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features nightly,unstable-traits \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features nightly \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features nightly,intrinsics \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features nightly,qspi-as-gpio \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,time-driver-any \

1
ci_stable.sh
View File

@ -36,6 +36,7 @@ cargo batch \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features unstable-traits,defmt \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features unstable-traits,log \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features qspi-as-gpio \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g473cc,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585zi,defmt,exti,time-driver-any,unstable-traits \

4
embassy-rp/Cargo.toml
View File

@ -42,6 +42,10 @@ boot2-ram-memcpy = []
boot2-w25q080 = []
boot2-w25x10cl = []
# Allow using QSPI pins as GPIO pins. This is mostly not what you want (because your flash lives there)
# and would add both code and memory overhead when enabled needlessly.
qspi-as-gpio = []
# Indicate code is running from RAM.
# Set this if all code is in RAM, and the cores never access memory-mapped flash memory through XIP.
# This allows the flash driver to not force pausing execution on both cores when doing flash operations.

8
embassy-rp/src/clocks.rs
View File

@ -702,7 +702,7 @@ impl<'d, T: Pin> Gpin<'d, T> {
pub fn new<P: GpinPin>(gpin: impl Peripheral<P = P> + 'd) -> Gpin<'d, P> {
into_ref!(gpin);
gpin.io().ctrl().write(|w| w.set_funcsel(0x08));
gpin.gpio().ctrl().write(|w| w.set_funcsel(0x08));
Gpin {
gpin: gpin.map_into(),
@ -718,7 +718,7 @@ impl<'d, T: Pin> Gpin<'d, T> {
impl<'d, T: Pin> Drop for Gpin<'d, T> {
fn drop(&mut self) {
self.gpin
.io()
.gpio()
.ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
}
@ -766,7 +766,7 @@ impl<'d, T: GpoutPin> Gpout<'d, T> {
pub fn new(gpout: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(gpout);
gpout.io().ctrl().write(|w| w.set_funcsel(0x08));
gpout.gpio().ctrl().write(|w| w.set_funcsel(0x08));
Self { gpout }
}
@ -831,7 +831,7 @@ impl<'d, T: GpoutPin> Drop for Gpout<'d, T> {
fn drop(&mut self) {
self.disable();
self.gpout
.io()
.gpio()
.ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
}

83
embassy-rp/src/gpio.rs
View File

@ -11,9 +11,13 @@ use crate::pac::common::{Reg, RW};
use crate::pac::SIO;
use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
const PIN_COUNT: usize = 30;
const NEW_AW: AtomicWaker = AtomicWaker::new();
static INTERRUPT_WAKERS: [AtomicWaker; PIN_COUNT] = [NEW_AW; PIN_COUNT];
const BANK0_PIN_COUNT: usize = 30;
static BANK0_WAKERS: [AtomicWaker; BANK0_PIN_COUNT] = [NEW_AW; BANK0_PIN_COUNT];
#[cfg(feature = "qspi-as-gpio")]
const QSPI_PIN_COUNT: usize = 6;
#[cfg(feature = "qspi-as-gpio")]
static QSPI_WAKERS: [AtomicWaker; QSPI_PIN_COUNT] = [NEW_AW; QSPI_PIN_COUNT];
/// Represents a digital input or output level.
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
@ -67,6 +71,7 @@ pub enum SlewRate {
#[derive(Debug, Eq, PartialEq)]
pub enum Bank {
Bank0 = 0,
#[cfg(feature = "qspi-as-gpio")]
Qspi = 1,
}
@ -140,17 +145,23 @@ pub(crate) unsafe fn init() {
interrupt::IO_IRQ_BANK0.disable();
interrupt::IO_IRQ_BANK0.set_priority(interrupt::Priority::P3);
interrupt::IO_IRQ_BANK0.enable();
#[cfg(feature = "qspi-as-gpio")]
{
interrupt::IO_IRQ_QSPI.disable();
interrupt::IO_IRQ_QSPI.set_priority(interrupt::Priority::P3);
interrupt::IO_IRQ_QSPI.enable();
}
}
#[cfg(feature = "rt")]
#[interrupt]
fn IO_IRQ_BANK0() {
fn irq_handler<const N: usize>(bank: pac::io::Io, wakers: &[AtomicWaker; N]) {
let cpu = SIO.cpuid().read() as usize;
// There are two sets of interrupt registers, one for cpu0 and one for cpu1
// and here we are selecting the set that belongs to the currently executing
// cpu.
let proc_intx: pac::io::Int = pac::IO_BANK0.int_proc(cpu);
for pin in 0..PIN_COUNT {
let proc_intx: pac::io::Int = bank.int_proc(cpu);
for pin in 0..N {
// There are 4 raw interrupt status registers, PROCx_INTS0, PROCx_INTS1,
// PROCx_INTS2, and PROCx_INTS3, and we are selecting the one that the
// current pin belongs to.
@ -171,11 +182,23 @@ fn IO_IRQ_BANK0() {
w.set_level_high(pin_group, true);
w.set_level_low(pin_group, true);
});
INTERRUPT_WAKERS[pin as usize].wake();
wakers[pin as usize].wake();
}
}
}
#[cfg(feature = "rt")]
#[interrupt]
fn IO_IRQ_BANK0() {
irq_handler(pac::IO_BANK0, &BANK0_WAKERS);
}
#[cfg(all(feature = "rt", feature = "qspi-as-gpio"))]
#[interrupt]
fn IO_IRQ_QSPI() {
irq_handler(pac::IO_QSPI, &QSPI_WAKERS);
}
#[must_use = "futures do nothing unless you `.await` or poll them"]
struct InputFuture<'a, T: Pin> {
pin: PeripheralRef<'a, T>,
@ -194,7 +217,7 @@ impl<'d, T: Pin> InputFuture<'d, T> {
// (the alternative being checking the current level and waiting for
// its inverse, but that requires reading the current level and thus
// missing anything that happened before the level was read.)
pac::IO_BANK0.intr(pin.pin() as usize / 8).write(|w| {
pin.io().intr(pin.pin() as usize / 8).write(|w| {
w.set_edge_high(pin_group, true);
w.set_edge_low(pin_group, true);
});
@ -234,7 +257,12 @@ impl<'d, T: Pin> Future for InputFuture<'d, T> {
fn poll(self: FuturePin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
// We need to register/re-register the waker for each poll because any
// calls to wake will deregister the waker.
INTERRUPT_WAKERS[self.pin.pin() as usize].register(cx.waker());
let waker = match self.pin.bank() {
Bank::Bank0 => &BANK0_WAKERS[self.pin.pin() as usize],
#[cfg(feature = "qspi-as-gpio")]
Bank::Qspi => &QSPI_WAKERS[self.pin.pin() as usize],
};
waker.register(cx.waker());
// self.int_proc() will get the register offset for the current cpu,
// then we want to access the interrupt enable register for our
@ -451,7 +479,7 @@ impl<'d, T: Pin> Flex<'d, T> {
w.set_ie(true);
});
pin.io().ctrl().write(|w| {
pin.gpio().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
});
@ -617,7 +645,7 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
#[inline]
fn drop(&mut self) {
self.pin.pad_ctrl().write(|_| {});
self.pin.io().ctrl().write(|w| {
self.pin.gpio().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _);
});
}
@ -636,24 +664,29 @@ pub(crate) mod sealed {
#[inline]
fn _bank(&self) -> Bank {
if self.pin_bank() & 0x20 == 0 {
Bank::Bank0
} else {
Bank::Qspi
match self.pin_bank() & 0x20 {
#[cfg(feature = "qspi-as-gpio")]
1 => Bank::Qspi,
_ => Bank::Bank0,
}
}
fn io(&self) -> pac::io::Gpio {
let block = match self._bank() {
fn io(&self) -> pac::io::Io {
match self._bank() {
Bank::Bank0 => crate::pac::IO_BANK0,
#[cfg(feature = "qspi-as-gpio")]
Bank::Qspi => crate::pac::IO_QSPI,
};
block.gpio(self._pin() as _)
}
}
fn gpio(&self) -> pac::io::Gpio {
self.io().gpio(self._pin() as _)
}
fn pad_ctrl(&self) -> Reg<pac::pads::regs::GpioCtrl, RW> {
let block = match self._bank() {
Bank::Bank0 => crate::pac::PADS_BANK0,
#[cfg(feature = "qspi-as-gpio")]
Bank::Qspi => crate::pac::PADS_QSPI,
};
block.gpio(self._pin() as _)
@ -672,12 +705,8 @@ pub(crate) mod sealed {
}
fn int_proc(&self) -> pac::io::Int {
let io_block = match self._bank() {
Bank::Bank0 => crate::pac::IO_BANK0,
Bank::Qspi => crate::pac::IO_QSPI,
};
let proc = SIO.cpuid().read();
io_block.int_proc(proc as _)
self.io().int_proc(proc as _)
}
}
}
@ -767,11 +796,17 @@ impl_pin!(PIN_27, Bank::Bank0, 27);
impl_pin!(PIN_28, Bank::Bank0, 28);
impl_pin!(PIN_29, Bank::Bank0, 29);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SCLK, Bank::Qspi, 0);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SS, Bank::Qspi, 1);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SD0, Bank::Qspi, 2);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SD1, Bank::Qspi, 3);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SD2, Bank::Qspi, 4);
#[cfg(feature = "qspi-as-gpio")]
impl_pin!(PIN_QSPI_SD3, Bank::Qspi, 5);
// ====================

4
embassy-rp/src/i2c.rs
View File

@ -353,8 +353,8 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
p.ic_rx_tl().write(|w| w.set_rx_tl(0));
// Configure SCL & SDA pins
scl.io().ctrl().write(|w| w.set_funcsel(3));
sda.io().ctrl().write(|w| w.set_funcsel(3));
scl.gpio().ctrl().write(|w| w.set_funcsel(3));
sda.gpio().ctrl().write(|w| w.set_funcsel(3));
scl.pad_ctrl().write(|w| {
w.set_schmitt(true);

2
embassy-rp/src/pio.rs
View File

@ -852,7 +852,7 @@ impl<'d, PIO: Instance> Common<'d, PIO> {
/// of [`Pio`] do not keep pin registrations alive.**
pub fn make_pio_pin(&mut self, pin: impl Peripheral<P = impl PioPin + 'd> + 'd) -> Pin<'d, PIO> {
into_ref!(pin);
pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _));
pin.gpio().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _));
// we can be relaxed about this because we're &mut here and nothing is cached
PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed);
Pin {

8
embassy-rp/src/pwm.rs
View File

@ -79,10 +79,10 @@ impl<'d, T: Channel> Pwm<'d, T> {
Self::configure(p, &config);
if let Some(pin) = &a {
pin.io().ctrl().write(|w| w.set_funcsel(4));
pin.gpio().ctrl().write(|w| w.set_funcsel(4));
}
if let Some(pin) = &b {
pin.io().ctrl().write(|w| w.set_funcsel(4));
pin.gpio().ctrl().write(|w| w.set_funcsel(4));
}
Self {
inner,
@ -243,10 +243,10 @@ impl<'d, T: Channel> Drop for Pwm<'d, T> {
fn drop(&mut self) {
self.inner.regs().csr().write_clear(|w| w.set_en(false));
if let Some(pin) = &self.pin_a {
pin.io().ctrl().write(|w| w.set_funcsel(31));
pin.gpio().ctrl().write(|w| w.set_funcsel(31));
}
if let Some(pin) = &self.pin_b {
pin.io().ctrl().write(|w| w.set_funcsel(31));
pin.gpio().ctrl().write(|w| w.set_funcsel(31));
}
}
}

8
embassy-rp/src/spi.rs
View File

@ -100,16 +100,16 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
p.cr1().write(|w| w.set_sse(true));
if let Some(pin) = &clk {
pin.io().ctrl().write(|w| w.set_funcsel(1));
pin.gpio().ctrl().write(|w| w.set_funcsel(1));
}
if let Some(pin) = &mosi {
pin.io().ctrl().write(|w| w.set_funcsel(1));
pin.gpio().ctrl().write(|w| w.set_funcsel(1));
}
if let Some(pin) = &miso {
pin.io().ctrl().write(|w| w.set_funcsel(1));
pin.gpio().ctrl().write(|w| w.set_funcsel(1));
}
if let Some(pin) = &cs {
pin.io().ctrl().write(|w| w.set_funcsel(1));
pin.gpio().ctrl().write(|w| w.set_funcsel(1));
}
Self {
inner,

8
embassy-rp/src/uart/mod.rs
View File

@ -565,7 +565,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
) {
let r = T::regs();
if let Some(pin) = &tx {
pin.io().ctrl().write(|w| {
pin.gpio().ctrl().write(|w| {
w.set_funcsel(2);
w.set_outover(if config.invert_tx {
Outover::INVERT
@ -576,7 +576,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true));
}
if let Some(pin) = &rx {
pin.io().ctrl().write(|w| {
pin.gpio().ctrl().write(|w| {
w.set_funcsel(2);
w.set_inover(if config.invert_rx {
Inover::INVERT
@ -587,7 +587,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true));
}
if let Some(pin) = &cts {
pin.io().ctrl().write(|w| {
pin.gpio().ctrl().write(|w| {
w.set_funcsel(2);
w.set_inover(if config.invert_cts {
Inover::INVERT
@ -598,7 +598,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
pin.pad_ctrl().write(|w| w.set_ie(true));
}
if let Some(pin) = &rts {
pin.io().ctrl().write(|w| {
pin.gpio().ctrl().write(|w| {
w.set_funcsel(2);
w.set_outover(if config.invert_rts {
Outover::INVERT