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fix(stm32): reorder dma and idle futures

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Badr Bouslikhin 2024-09-06 18:35:23 +02:00
parent f0a8607051
commit ee25f14b20
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1 changed files with 17 additions and 17 deletions
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34
embassy-stm32/src/usart/ringbuffered.rs
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@ -184,20 +184,6 @@ impl<'d> RingBufferedUartRx<'d> {
async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> { async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> {
compiler_fence(Ordering::SeqCst); compiler_fence(Ordering::SeqCst);
let mut dma_init = false;
// Future which completes when there is dma is half full or full
let dma = poll_fn(|cx| {
self.ring_buf.set_waker(cx.waker());
let status = match dma_init {
false => Poll::Pending,
true => Poll::Ready(()),
};
dma_init = true;
status
});
// Future which completes when idle line is detected // Future which completes when idle line is detected
let s = self.state; let s = self.state;
let uart = poll_fn(|cx| { let uart = poll_fn(|cx| {
@ -219,9 +205,23 @@ impl<'d> RingBufferedUartRx<'d> {
} }
}); });
match select(dma, uart).await { let mut dma_init = false;
Either::Left(((), _)) => Ok(()), // Future which completes when there is dma is half full or full
Either::Right((result, _)) => result, let dma = poll_fn(|cx| {
self.ring_buf.set_waker(cx.waker());
let status = match dma_init {
false => Poll::Pending,
true => Poll::Ready(()),
};
dma_init = true;
status
});
match select(uart, dma).await {
Either::Left((result, _)) => result,
Either::Right(((), _)) => Ok(()),
} }
} }
} }