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fix: flush SAI FIFO on init

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This commit is contained in:
elagil 2024-11-15 00:07:23 +01:00
parent 4692f06c33
commit edb9b03dee
1 changed files with 4 additions and 2 deletions
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6
embassy-stm32/src/sai/mod.rs
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@ -861,12 +861,15 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
ring_buffer: RingBuffer<'d, W>,
config: Config,
) -> Self {
let ch = T::REGS.ch(sub_block as usize);
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
{
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
}
ch.cr2().modify(|w| w.set_fflush(true));
#[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
{
if let SyncInput::External(i) = config.sync_input {
@ -888,7 +891,6 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
{
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| {
w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
TxRx::Transmitter