From ecdd7c0e2f9dcc07e53e136557140d3ccc6a5ee1 Mon Sep 17 00:00:00 2001 From: pbert Date: Wed, 11 Oct 2023 21:38:41 +0200 Subject: [PATCH] enable clock first --- embassy-stm32/build.rs | 4 ++-- embassy-stm32/src/adc/f1.rs | 2 +- embassy-stm32/src/adc/f3.rs | 2 +- embassy-stm32/src/adc/v1.rs | 2 +- embassy-stm32/src/adc/v2.rs | 2 +- embassy-stm32/src/adc/v3.rs | 2 +- embassy-stm32/src/adc/v4.rs | 2 +- embassy-stm32/src/can/bxcan.rs | 2 +- embassy-stm32/src/crc/v1.rs | 2 +- embassy-stm32/src/crc/v2v3.rs | 2 +- embassy-stm32/src/dac/mod.rs | 8 ++++---- embassy-stm32/src/dcmi.rs | 2 +- embassy-stm32/src/fmc.rs | 2 +- embassy-stm32/src/gpio.rs | 2 +- embassy-stm32/src/hrtim/mod.rs | 2 +- embassy-stm32/src/i2c/v1.rs | 2 +- embassy-stm32/src/i2c/v2.rs | 2 +- embassy-stm32/src/ipcc.rs | 2 +- embassy-stm32/src/lib.rs | 6 +++--- embassy-stm32/src/qspi/mod.rs | 2 +- embassy-stm32/src/rcc/g4.rs | 2 +- embassy-stm32/src/rcc/mod.rs | 2 +- embassy-stm32/src/rng.rs | 2 +- embassy-stm32/src/rtc/mod.rs | 2 +- embassy-stm32/src/sai/mod.rs | 4 ++-- embassy-stm32/src/sdmmc/mod.rs | 2 +- embassy-stm32/src/spi/mod.rs | 2 +- embassy-stm32/src/time_driver.rs | 2 +- embassy-stm32/src/timer/complementary_pwm.rs | 2 +- embassy-stm32/src/timer/qei.rs | 2 +- embassy-stm32/src/timer/simple_pwm.rs | 2 +- embassy-stm32/src/usart/buffered.rs | 12 +++++------ embassy-stm32/src/usart/mod.rs | 20 +++++++++---------- embassy-stm32/src/usb/usb.rs | 2 +- embassy-stm32/src/usb_otg/usb.rs | 2 +- examples/stm32h7/src/bin/dac_dma.rs | 4 ++-- .../stm32h7/src/bin/low_level_timer_api.rs | 2 +- examples/stm32l4/src/bin/dac_dma.rs | 4 ++-- 38 files changed, 61 insertions(+), 61 deletions(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 719a52d1d..63cf6b21f 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -556,14 +556,14 @@ fn main() { fn frequency() -> crate::time::Hertz { #clock_frequency } - fn enable() { + fn enable_and_reset() { critical_section::with(|_cs| { #before_enable - #rst #[cfg(feature = "low-power")] crate::rcc::clock_refcount_add(_cs); crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true)); #after_enable + #rst }) } fn disable() { diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs index 5f5bf4bfa..ad0f13826 100644 --- a/embassy-stm32/src/adc/f1.rs +++ b/embassy-stm32/src/adc/f1.rs @@ -51,7 +51,7 @@ impl super::sealed::AdcPin for Temperature { impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: impl Peripheral

+ 'd, delay: &mut impl DelayUs) -> Self { into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); T::regs().cr2().modify(|reg| reg.set_adon(true)); // 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’) diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs index e94f61413..6f59c230f 100644 --- a/embassy-stm32/src/adc/f3.rs +++ b/embassy-stm32/src/adc/f3.rs @@ -64,7 +64,7 @@ impl<'d, T: Instance> Adc<'d, T> { into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); // Enable the adc regulator T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE)); diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs index f03acdcf4..852b027df 100644 --- a/embassy-stm32/src/adc/v1.rs +++ b/embassy-stm32/src/adc/v1.rs @@ -61,7 +61,7 @@ impl<'d, T: Instance> Adc<'d, T> { delay: &mut impl DelayUs, ) -> Self { into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); // Delay 1μs when using HSI14 as the ADC clock. // diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs index 89e7616bc..eda1324de 100644 --- a/embassy-stm32/src/adc/v2.rs +++ b/embassy-stm32/src/adc/v2.rs @@ -95,7 +95,7 @@ where { pub fn new(adc: impl Peripheral

+ 'd, delay: &mut impl DelayUs) -> Self { into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); let presc = Prescaler::from_pclk2(T::frequency()); T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre())); diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index e50e6482c..281a99f72 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -48,7 +48,7 @@ impl super::sealed::AdcPin for Vbat { impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: impl Peripheral

+ 'd, delay: &mut impl DelayUs) -> Self { into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); T::regs().cr().modify(|reg| { #[cfg(not(adc_g0))] reg.set_deeppwd(false); diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs index 6d86e5cdf..d74617cb3 100644 --- a/embassy-stm32/src/adc/v4.rs +++ b/embassy-stm32/src/adc/v4.rs @@ -127,7 +127,7 @@ impl Prescaler { impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: impl Peripheral

+ 'd, delay: &mut impl DelayUs) -> Self { embassy_hal_internal::into_ref!(adc); - T::reset_and_enable(); + T::enable_and_reset(); let prescaler = Prescaler::from_ker_ck(T::frequency()); diff --git a/embassy-stm32/src/can/bxcan.rs b/embassy-stm32/src/can/bxcan.rs index 903f7e48b..0d4bf692d 100644 --- a/embassy-stm32/src/can/bxcan.rs +++ b/embassy-stm32/src/can/bxcan.rs @@ -136,7 +136,7 @@ impl<'d, T: Instance> Can<'d, T> { rx.set_as_af(rx.af_num(), AFType::Input); tx.set_as_af(tx.af_num(), AFType::OutputPushPull); - T::reset_and_enable(); + T::enable_and_reset(); { use crate::pac::can::vals::{Errie, Fmpie, Tmeie}; diff --git a/embassy-stm32/src/crc/v1.rs b/embassy-stm32/src/crc/v1.rs index 282e1ad88..c0f580830 100644 --- a/embassy-stm32/src/crc/v1.rs +++ b/embassy-stm32/src/crc/v1.rs @@ -16,7 +16,7 @@ impl<'d> Crc<'d> { // Note: enable and reset come from RccPeripheral. // enable CRC clock in RCC. - CRC::reset_and_enable(); + CRC::enable_and_reset(); // Peripheral the peripheral let mut instance = Self { _peri: peripheral }; instance.reset(); diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs index 2ab25e6fb..b36f6018c 100644 --- a/embassy-stm32/src/crc/v2v3.rs +++ b/embassy-stm32/src/crc/v2v3.rs @@ -70,7 +70,7 @@ impl<'d> Crc<'d> { pub fn new(peripheral: impl Peripheral

+ 'd, config: Config) -> Self { // Note: enable and reset come from RccPeripheral. // reset to default values and enable CRC clock in RCC. - CRC::reset_and_enable(); + CRC::enable_and_reset(); into_ref!(peripheral); let mut instance = Self { _peripheral: peripheral, diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs index e93fca954..6458572f2 100644 --- a/embassy-stm32/src/dac/mod.rs +++ b/embassy-stm32/src/dac/mod.rs @@ -255,7 +255,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> { ) -> Self { pin.set_as_analog(); into_ref!(peri, dma); - T::reset_and_enable(); + T::enable_and_reset(); let mut dac = Self { _peri: peri, dma }; @@ -365,7 +365,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> { ) -> Self { pin.set_as_analog(); into_ref!(_peri, dma); - T::reset_and_enable(); + T::enable_and_reset(); let mut dac = Self { phantom: PhantomData, @@ -481,7 +481,7 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> { pin_ch1.set_as_analog(); pin_ch2.set_as_analog(); into_ref!(peri, dma_ch1, dma_ch2); - T::reset_and_enable(); + T::enable_and_reset(); let mut dac_ch1 = DacCh1 { _peri: peri, @@ -567,7 +567,7 @@ foreach_peripheral!( critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 }) } - fn reset_and_enable() { + fn enable_and_reset() { critical_section::with(|_| { crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true)); crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false)); diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs index 6a63e6ee5..b12230794 100644 --- a/embassy-stm32/src/dcmi.rs +++ b/embassy-stm32/src/dcmi.rs @@ -330,7 +330,7 @@ where use_embedded_synchronization: bool, edm: u8, ) -> Self { - T::reset_and_enable(); + T::enable_and_reset(); peri.regs().cr().modify(|r| { r.set_cm(true); // disable continuous mode (snapshot mode) diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs index 51c75aeb3..d6e25996c 100644 --- a/embassy-stm32/src/fmc.rs +++ b/embassy-stm32/src/fmc.rs @@ -19,7 +19,7 @@ where const REGISTERS: *const () = T::REGS.as_ptr() as *const _; fn enable(&mut self) { - T::reset_and_enable(); + T::enable_and_reset(); } fn memory_controller_enable(&mut self) { diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs index 9192f731f..37fedf8e1 100644 --- a/embassy-stm32/src/gpio.rs +++ b/embassy-stm32/src/gpio.rs @@ -759,7 +759,7 @@ foreach_pin!( pub(crate) unsafe fn init() { #[cfg(afio)] - ::reset_and_enable(); + ::enable_and_reset(); crate::_generated::init_gpio(); } diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs index 0c730ef7e..17096d48c 100644 --- a/embassy-stm32/src/hrtim/mod.rs +++ b/embassy-stm32/src/hrtim/mod.rs @@ -157,7 +157,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> { fn new_inner(tim: impl Peripheral

+ 'd) -> Self { into_ref!(tim); - T::reset_and_enable(); + T::enable_and_reset(); #[cfg(stm32f334)] if unsafe { get_freqs() }.hrtim.is_some() { diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs index cc2b23a7f..ab59f5ab9 100644 --- a/embassy-stm32/src/i2c/v1.rs +++ b/embassy-stm32/src/i2c/v1.rs @@ -56,7 +56,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { ) -> Self { into_ref!(scl, sda, tx_dma, rx_dma); - T::reset_and_enable(); + T::enable_and_reset(); scl.set_as_af_pull( scl.af_num(), diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs index 1a49ecb24..b6d880d57 100644 --- a/embassy-stm32/src/i2c/v2.rs +++ b/embassy-stm32/src/i2c/v2.rs @@ -86,7 +86,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> { ) -> Self { into_ref!(peri, scl, sda, tx_dma, rx_dma); - T::reset_and_enable(); + T::enable_and_reset(); scl.set_as_af_pull( scl.af_num(), diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs index 2e58fe622..1b1e182f0 100644 --- a/embassy-stm32/src/ipcc.rs +++ b/embassy-stm32/src/ipcc.rs @@ -93,7 +93,7 @@ pub struct Ipcc; impl Ipcc { pub fn enable(_config: Config) { - IPCC::reset_and_enable(); + IPCC::enable_and_reset(); IPCC::set_cpu2(true); _configure_pwr(); diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 438494223..b93e5ee87 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -186,11 +186,11 @@ pub fn init(config: Config) -> Peripherals { } #[cfg(not(any(stm32f1, stm32wb, stm32wl)))] - peripherals::SYSCFG::reset_and_enable(); + peripherals::SYSCFG::enable_and_reset(); #[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))] - peripherals::PWR::reset_and_enable(); + peripherals::PWR::enable_and_reset(); #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))] - peripherals::FLASH::reset_and_enable(); + peripherals::FLASH::enable_and_reset(); unsafe { #[cfg(feature = "_split-pins-enabled")] diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 1c8bcbae9..4b0e8ecef 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs @@ -177,7 +177,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { ) -> Self { into_ref!(peri, dma); - T::reset_and_enable(); + T::enable_and_reset(); while T::REGS.sr().read().busy() {} diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs index 1b6b5e85e..afdf5cc73 100644 --- a/embassy-stm32/src/rcc/g4.rs +++ b/embassy-stm32/src/rcc/g4.rs @@ -296,7 +296,7 @@ pub(crate) unsafe fn init(config: Config) { // Enable and setup CRS if needed if let Some(crs_config) = crs_config { - crate::peripherals::CRS::reset_and_enable(); + crate::peripherals::CRS::enable_and_reset(); let sync_src = match crs_config.sync_src { CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO, diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 451e12fec..0263c97aa 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -231,7 +231,7 @@ pub mod low_level { pub(crate) mod sealed { pub trait RccPeripheral { fn frequency() -> crate::time::Hertz; - fn reset_and_enable(); + fn enable_and_reset(); fn disable(); } } diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs index 0a3b966b6..fc003ebe6 100644 --- a/embassy-stm32/src/rng.rs +++ b/embassy-stm32/src/rng.rs @@ -43,7 +43,7 @@ impl<'d, T: Instance> Rng<'d, T> { inner: impl Peripheral

+ 'd, _irq: impl interrupt::typelevel::Binding> + 'd, ) -> Self { - T::reset_and_enable(); + T::enable_and_reset(); into_ref!(inner); let mut random = Self { _inner: inner }; random.reset(); diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs index 2eb0cde14..552dcc76f 100644 --- a/embassy-stm32/src/rtc/mod.rs +++ b/embassy-stm32/src/rtc/mod.rs @@ -184,7 +184,7 @@ impl Default for RtcCalibrationCyclePeriod { impl Rtc { pub fn new(_rtc: impl Peripheral

, rtc_config: RtcConfig) -> Self { #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))] - ::reset_and_enable(); + ::enable_and_reset(); let mut this = Self { #[cfg(feature = "low-power")] diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs index a394ba717..a0b4ddac7 100644 --- a/embassy-stm32/src/sai/mod.rs +++ b/embassy-stm32/src/sai/mod.rs @@ -580,7 +580,7 @@ fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>( impl<'d, T: Instance> Sai<'d, T> { pub fn new(peri: impl Peripheral

+ 'd) -> Self { - T::reset_and_enable(); + T::enable_and_reset(); Self { _peri: unsafe { peri.clone_unchecked().into_ref() }, @@ -960,7 +960,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> { } pub fn reset() { - T::reset_and_enable(); + T::enable_and_reset(); } pub fn flush(&mut self) { diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs index 595d2c199..bc29fe549 100644 --- a/embassy-stm32/src/sdmmc/mod.rs +++ b/embassy-stm32/src/sdmmc/mod.rs @@ -452,7 +452,7 @@ impl<'d, T: Instance, Dma: SdmmcDma + 'd> Sdmmc<'d, T, Dma> { ) -> Self { into_ref!(sdmmc, dma); - T::reset_and_enable(); + T::enable_and_reset(); T::Interrupt::unpend(); unsafe { T::Interrupt::enable() }; diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index ea7132e06..211b55231 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -230,7 +230,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { let lsbfirst = config.raw_byte_order(); - T::reset_and_enable(); + T::enable_and_reset(); #[cfg(any(spi_v1, spi_f1))] { diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs index 1468d9b6a..baea20aef 100644 --- a/embassy-stm32/src/time_driver.rs +++ b/embassy-stm32/src/time_driver.rs @@ -155,7 +155,7 @@ impl RtcDriver { fn init(&'static self) { let r = T::regs_gp16(); - ::reset_and_enable(); + ::enable_and_reset(); let timer_freq = T::frequency(); diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs index 3818cc03c..9349a6fad 100644 --- a/embassy-stm32/src/timer/complementary_pwm.rs +++ b/embassy-stm32/src/timer/complementary_pwm.rs @@ -64,7 +64,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> { fn new_inner(tim: impl Peripheral

+ 'd, freq: Hertz) -> Self { into_ref!(tim); - T::reset_and_enable(); + T::enable_and_reset(); let mut this = Self { inner: tim }; diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs index ecc9fabc7..01d028bf9 100644 --- a/embassy-stm32/src/timer/qei.rs +++ b/embassy-stm32/src/timer/qei.rs @@ -55,7 +55,7 @@ impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> { fn new_inner(tim: impl Peripheral

+ 'd) -> Self { into_ref!(tim); - T::reset_and_enable(); + T::enable_and_reset(); // Configure TxC1 and TxC2 as captures T::regs_gp16().ccmr_input(0).modify(|w| { diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 83c812775..18ecc1964 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -63,7 +63,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> { fn new_inner(tim: impl Peripheral

+ 'd, freq: Hertz) -> Self { into_ref!(tim); - T::reset_and_enable(); + T::enable_and_reset(); let mut this = Self { inner: tim }; diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index b4a74dc46..82d925a43 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -152,8 +152,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { config: Config, ) -> Result { // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config) } @@ -172,8 +172,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { into_ref!(cts, rts); // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); rts.set_as_af(rts.af_num(), AFType::OutputPushPull); cts.set_as_af(cts.af_num(), AFType::Input); @@ -199,8 +199,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { into_ref!(de); // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); de.set_as_af(de.af_num(), AFType::OutputPushPull); T::regs().cr3().write(|w| { diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 93e21ccb6..3b7f5184d 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -228,7 +228,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> { tx_dma: impl Peripheral

+ 'd, config: Config, ) -> Result { - T::reset_and_enable(); + T::enable_and_reset(); Self::new_inner(peri, tx, tx_dma, config) } @@ -242,7 +242,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> { ) -> Result { into_ref!(cts); - T::reset_and_enable(); + T::enable_and_reset(); cts.set_as_af(cts.af_num(), AFType::Input); T::regs().cr3().write(|w| { @@ -319,7 +319,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> { rx_dma: impl Peripheral

+ 'd, config: Config, ) -> Result { - T::reset_and_enable(); + T::enable_and_reset(); Self::new_inner(peri, rx, rx_dma, config) } @@ -334,7 +334,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> { ) -> Result { into_ref!(rts); - T::reset_and_enable(); + T::enable_and_reset(); rts.set_as_af(rts.af_num(), AFType::OutputPushPull); T::regs().cr3().write(|w| { @@ -691,8 +691,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> { config: Config, ) -> Result { // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config) } @@ -711,8 +711,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> { into_ref!(cts, rts); // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); rts.set_as_af(rts.af_num(), AFType::OutputPushPull); cts.set_as_af(cts.af_num(), AFType::Input); @@ -737,8 +737,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> { into_ref!(de); // UartRx and UartTx have one refcount ea. - T::reset_and_enable(); - T::reset_and_enable(); + T::enable_and_reset(); + T::enable_and_reset(); de.set_as_af(de.af_num(), AFType::OutputPushPull); T::regs().cr3().write(|w| { diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs index d05207d1d..9269ddd88 100644 --- a/embassy-stm32/src/usb/usb.rs +++ b/embassy-stm32/src/usb/usb.rs @@ -269,7 +269,7 @@ impl<'d, T: Instance> Driver<'d, T> { #[cfg(pwr_h5)] crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true)); - ::reset_and_enable(); + ::enable_and_reset(); regs.cntr().write(|w| { w.set_pdwn(false); diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs index 9edffa901..e45e4ac43 100644 --- a/embassy-stm32/src/usb_otg/usb.rs +++ b/embassy-stm32/src/usb_otg/usb.rs @@ -632,7 +632,7 @@ impl<'d, T: Instance> Bus<'d, T> { }); } - ::reset_and_enable(); + ::enable_and_reset(); T::Interrupt::unpend(); unsafe { T::Interrupt::enable() }; diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs index 5f3afbafa..334986a05 100644 --- a/examples/stm32h7/src/bin/dac_dma.rs +++ b/examples/stm32h7/src/bin/dac_dma.rs @@ -79,7 +79,7 @@ async fn dac_task1(mut dac: Dac1Type) { dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); dac.enable_channel().unwrap(); - TIM6::reset_and_enable(); + TIM6::enable_and_reset(); TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM6::regs().cr1().modify(|w| { @@ -118,7 +118,7 @@ async fn dac_task2(mut dac: Dac2Type) { error!("Reload value {} below threshold!", reload); } - TIM7::reset_and_enable(); + TIM7::enable_and_reset(); TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM7::regs().cr1().modify(|w| { diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index 757ee3286..5841efb24 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs @@ -73,7 +73,7 @@ impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> { ) -> Self { into_ref!(tim, ch1, ch2, ch3, ch4); - T::reset_and_enable(); + T::enable_and_reset(); ch1.set_speed(Speed::VeryHigh); ch1.set_as_af(ch1.af_num(), AFType::OutputPushPull); diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs index 83d48f221..98f37f906 100644 --- a/examples/stm32l4/src/bin/dac_dma.rs +++ b/examples/stm32l4/src/bin/dac_dma.rs @@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) { dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); dac.enable_channel().unwrap(); - TIM6::reset_and_enable(); + TIM6::enable_and_reset(); TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM6::regs().cr1().modify(|w| { @@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) { error!("Reload value {} below threshold!", reload); } - TIM7::reset_and_enable(); + TIM7::enable_and_reset(); TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); TIM7::regs().cr1().modify(|w| {