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Expose rx_delay in nrf qspi config

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ftilde 2024-01-04 21:24:09 +01:00
parent 51de518bd3
commit eb70d744a9
1 changed files with 8 additions and 0 deletions
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8
embassy-nrf/src/qspi.rs
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@ -80,6 +80,8 @@ pub struct Config {
pub frequency: Frequency, pub frequency: Frequency,
/// Value is specified in number of 16 MHz periods (62.5 ns) /// Value is specified in number of 16 MHz periods (62.5 ns)
pub sck_delay: u8, pub sck_delay: u8,
/// Value is specified in number of 64 MHz periods (15.625 ns), valid values between 0 and 7 (inclusive)
pub rx_delay: u8,
/// Whether data is captured on the clock rising edge and data is output on a falling edge (MODE0) or vice-versa (MODE3) /// Whether data is captured on the clock rising edge and data is output on a falling edge (MODE0) or vice-versa (MODE3)
pub spi_mode: SpiMode, pub spi_mode: SpiMode,
/// Addressing mode (24-bit or 32-bit) /// Addressing mode (24-bit or 32-bit)
@ -98,6 +100,7 @@ impl Default for Config {
deep_power_down: None, deep_power_down: None,
frequency: Frequency::M8, frequency: Frequency::M8,
sck_delay: 80, sck_delay: 80,
rx_delay: 2,
spi_mode: SpiMode::MODE0, spi_mode: SpiMode::MODE0,
address_mode: AddressMode::_24BIT, address_mode: AddressMode::_24BIT,
capacity: 0, capacity: 0,
@ -202,6 +205,11 @@ impl<'d, T: Instance> Qspi<'d, T> {
w w
}); });
r.iftiming.write(|w| unsafe {
w.rxdelay().bits(config.rx_delay & 0b111);
w
});
r.xipoffset.write(|w| unsafe { r.xipoffset.write(|w| unsafe {
w.xipoffset().bits(config.xip_offset); w.xipoffset().bits(config.xip_offset);
w w