nordic-dev.net/embassy
2
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2024-11-25 08:12:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

Use defmt-friendly error handling

Browse Source
This commit is contained in:
Joonas Javanainen 2022-04-30 11:41:17 +03:00
parent 1d5f9b86fb
commit e88559c5ca
No known key found for this signature in database
GPG Key ID: D39CCA5CB19B9179
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
embassy-stm32/src/rcc/f2.rs
View File

@ -424,10 +424,10 @@ pub(crate) unsafe fn init(config: Config) {
let pll_src_freq = match config.pll_mux {
PLLSrc::HSE => {
config
let hse_config = config
.hse
.expect("HSE must be configured to be used as PLL input")
.frequency
.unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
hse_config.frequency
}
PLLSrc::HSI => HSI,
};
@ -458,7 +458,7 @@ pub(crate) unsafe fn init(config: Config) {
ClockSrc::HSE => {
let hse_config = config
.hse
.expect("HSE must be configured to be used as system clock");
.unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
(hse_config.frequency, Sw::HSE)
}
ClockSrc::PLL => {
@ -475,7 +475,7 @@ pub(crate) unsafe fn init(config: Config) {
// Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
assert!(ahb_freq <= Hertz(120_000_000));
let flash_ws = config.voltage.wait_states(ahb_freq).expect("Invalid HCLK");
let flash_ws = unwrap!(config.voltage.wait_states(ahb_freq));
FLASH.acr().modify(|w| w.set_latency(flash_ws));
RCC.cfgr().modify(|w| {

6
examples/stm32f2/src/bin/pll.rs
View File

@ -30,13 +30,13 @@ fn config() -> Config {
config.rcc.pll_mux = PLLSrc::HSE;
config.rcc.pll = PLLConfig {
// 8 MHz clock source / 8 = 1 MHz PLL input
pre_div: PLLPreDiv::try_from(8).unwrap(),
pre_div: unwrap!(PLLPreDiv::try_from(8)),
// 1 MHz PLL input * 240 = 240 MHz PLL VCO
mul: PLLMul::try_from(240).unwrap(),
mul: unwrap!(PLLMul::try_from(240)),
// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
main_div: PLLMainDiv::Div2,
// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
pll48_div: PLL48Div::try_from(5).unwrap(),
pll48_div: unwrap!(PLL48Div::try_from(5)),
};
// System clock comes from PLL (= the 120 MHz main PLL output)
config.rcc.mux = ClockSrc::PLL;