mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-25 00:02:28 +00:00
stm32/qspi: remove DMA generic param.
This commit is contained in:
Dario Nieuwenhuis
parent
6fa608f516
commit
e7161aa085
@ -4,11 +4,14 @@
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pub mod enums;
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use enums::*;
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use crate::dma::Transfer;
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use crate::gpio::{AFType, AnyPin, Pull};
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use crate::dma::ChannelAndRequest;
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use crate::gpio::{AFType, AnyPin, Pull, Speed};
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use crate::mode::{Async, Blocking, Mode as PeriMode};
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use crate::pac::quadspi::Quadspi as Regs;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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@ -71,7 +74,7 @@ impl Default for Config {
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/// QSPI driver.
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#[allow(dead_code)]
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pub struct Qspi<'d, T: Instance, Dma> {
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pub struct Qspi<'d, T: Instance, M: PeriMode> {
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_peri: PeripheralRef<'d, T>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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@ -79,93 +82,12 @@ pub struct Qspi<'d, T: Instance, Dma> {
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: PeripheralRef<'d, Dma>,
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dma: Option<ChannelAndRequest<'d>>,
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_phantom: PhantomData<M>,
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config: Config,
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}
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impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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/// Create a new QSPI driver for bank 1.
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pub fn new_bk1(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, d0, d1, d2, d3, sck, nss);
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sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up);
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nss.set_speed(crate::gpio::Speed::VeryHigh);
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d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None);
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d0.set_speed(crate::gpio::Speed::VeryHigh);
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d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None);
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d1.set_speed(crate::gpio::Speed::VeryHigh);
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d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None);
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d2.set_speed(crate::gpio::Speed::VeryHigh);
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d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None);
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d3.set_speed(crate::gpio::Speed::VeryHigh);
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Self::new_inner(
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peri,
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Some(d0.map_into()),
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Some(d1.map_into()),
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Some(d2.map_into()),
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Some(d3.map_into()),
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Some(sck.map_into()),
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Some(nss.map_into()),
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dma,
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config,
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FlashSelection::Flash1,
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)
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}
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/// Create a new QSPI driver for bank 2.
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pub fn new_bk2(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, d0, d1, d2, d3, sck, nss);
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sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, Pull::None);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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nss.set_as_af_pull(nss.af_num(), AFType::OutputPushPull, Pull::Up);
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nss.set_speed(crate::gpio::Speed::VeryHigh);
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d0.set_as_af_pull(d0.af_num(), AFType::OutputPushPull, Pull::None);
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d0.set_speed(crate::gpio::Speed::VeryHigh);
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d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None);
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d1.set_speed(crate::gpio::Speed::VeryHigh);
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d2.set_as_af_pull(d2.af_num(), AFType::OutputPushPull, Pull::None);
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d2.set_speed(crate::gpio::Speed::VeryHigh);
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d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None);
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d3.set_speed(crate::gpio::Speed::VeryHigh);
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Self::new_inner(
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peri,
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Some(d0.map_into()),
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Some(d1.map_into()),
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Some(d2.map_into()),
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Some(d3.map_into()),
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Some(sck.map_into()),
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Some(nss.map_into()),
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dma,
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config,
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FlashSelection::Flash2,
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)
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}
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impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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@ -174,11 +96,11 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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d3: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: impl Peripheral<P = Dma> + 'd,
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dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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fsel: FlashSelection,
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) -> Self {
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into_ref!(peri, dma);
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into_ref!(peri);
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T::enable_and_reset();
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@ -220,6 +142,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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d3,
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nss,
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dma,
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_phantom: PhantomData,
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config,
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}
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}
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@ -278,68 +201,6 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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/// Blocking read data, using DMA.
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pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig)
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where
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Dma: QuadDma<T>,
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{
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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let request = self.dma.request();
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let transfer = unsafe {
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Transfer::new_read(
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&mut self.dma,
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request,
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T::REGS.dr().as_ptr() as *mut u8,
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buf,
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Default::default(),
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)
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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/// Blocking write data, using DMA.
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pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig)
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where
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Dma: QuadDma<T>,
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{
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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let request = self.dma.request();
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let transfer = unsafe {
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Transfer::new_write(
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&mut self.dma,
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request,
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buf,
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T::REGS.dr().as_ptr() as *mut u8,
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Default::default(),
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)
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig, data_len: Option<usize>) {
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T::REGS.fcr().modify(|v| {
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v.set_csmf(true);
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@ -373,6 +234,160 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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}
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}
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impl<'d, T: Instance> Qspi<'d, T, Blocking> {
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/// Create a new QSPI driver for bank 1, in blocking mode.
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pub fn new_blocking_bank1(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d1, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d2, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d3, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(nss, AFType::OutputPushPull, Speed::VeryHigh, Pull::Up),
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None,
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config,
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FlashSelection::Flash1,
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)
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}
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/// Create a new QSPI driver for bank 2, in blocking mode.
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pub fn new_blocking_bank2(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d1, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d2, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d3, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(nss, AFType::OutputPushPull, Speed::VeryHigh, Pull::Up),
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None,
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config,
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FlashSelection::Flash2,
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)
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}
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}
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impl<'d, T: Instance> Qspi<'d, T, Async> {
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/// Create a new QSPI driver for bank 1.
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pub fn new_bank1(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
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dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d1, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d2, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d3, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(nss, AFType::OutputPushPull, Speed::VeryHigh, Pull::Up),
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new_dma!(dma),
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config,
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FlashSelection::Flash1,
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)
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}
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/// Create a new QSPI driver for bank 2.
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pub fn new_bank2(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
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dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d1, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d2, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(d3, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh),
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new_pin!(nss, AFType::OutputPushPull, Speed::VeryHigh, Pull::Up),
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new_dma!(dma),
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config,
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FlashSelection::Flash2,
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)
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}
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/// Blocking read data, using DMA.
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pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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let transfer = unsafe {
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self.dma
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.as_mut()
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.unwrap()
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.read(T::REGS.dr().as_ptr() as *mut u8, buf, Default::default())
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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/// Blocking write data, using DMA.
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pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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let transfer = unsafe {
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self.dma
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.as_mut()
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.unwrap()
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.write(buf, T::REGS.dr().as_ptr() as *mut u8, Default::default())
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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}
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trait SealedInstance {
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const REGS: Regs;
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}
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@ -4,8 +4,9 @@
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use defmt::info;
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use embassy_executor::Spawner;
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use embassy_stm32::mode::Async;
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use embassy_stm32::qspi::enums::{AddressSize, ChipSelectHighTime, FIFOThresholdLevel, MemorySize, *};
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use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, QuadDma, TransferConfig};
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use embassy_stm32::qspi::{Config as QspiCfg, Instance, Qspi, TransferConfig};
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use embassy_stm32::time::mhz;
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use embassy_stm32::Config as StmCfg;
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use {defmt_rtt as _, panic_probe as _};
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@ -43,12 +44,12 @@ const MEMORY_ADDR: u32 = 0x00000000u32;
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/// Implementation of access to flash chip.
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/// Chip commands are hardcoded as it depends on used chip.
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/// This implementation is using chip GD25Q64C from Giga Device
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pub struct FlashMemory<I: Instance, D: QuadDma<I>> {
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qspi: Qspi<'static, I, D>,
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pub struct FlashMemory<I: Instance> {
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qspi: Qspi<'static, I, Async>,
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}
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impl<I: Instance, D: QuadDma<I>> FlashMemory<I, D> {
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pub fn new(qspi: Qspi<'static, I, D>) -> Self {
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impl<I: Instance> FlashMemory<I> {
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pub fn new(qspi: Qspi<'static, I, Async>) -> Self {
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let mut memory = Self { qspi };
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memory.reset_memory();
|
||||
@ -279,7 +280,7 @@ async fn main(_spawner: Spawner) -> ! {
|
||||
cs_high_time: ChipSelectHighTime::_1Cycle,
|
||||
fifo_threshold: FIFOThresholdLevel::_16Bytes,
|
||||
};
|
||||
let driver = Qspi::new_bk1(
|
||||
let driver = Qspi::new_bank1(
|
||||
p.QUADSPI, p.PF8, p.PF9, p.PE2, p.PF6, p.PF10, p.PB10, p.DMA2_CH7, config,
|
||||
);
|
||||
let mut flash = FlashMemory::new(driver);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user