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STM32 SPI: Set clk-pin pull-up/-down to match spi clock polarity
RM0394: 40.4.6 Communication formats ... The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
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@ -10,7 +10,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
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use self::sealed::WordSize;
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use crate::dma::{slice_ptr_parts, Transfer};
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::gpio::{AnyPin, Pull};
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use crate::pac::spi::{regs, vals, Spi as Regs};
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use crate::rcc::RccPeripheral;
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use crate::time::Hertz;
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@ -93,8 +93,14 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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config: Config,
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) -> Self {
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into_ref!(peri, sck, mosi, miso);
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let sck_pull_mode = match config.mode.polarity {
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Polarity::IdleLow => Pull::Down,
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Polarity::IdleHigh => Pull::Up,
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};
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unsafe {
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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sck.set_as_af_pull(sck.af_num(), AFType::OutputPushPull, sck_pull_mode);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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mosi.set_as_af(mosi.af_num(), AFType::OutputPushPull);
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mosi.set_speed(crate::gpio::Speed::VeryHigh);
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