mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-22 06:42:32 +00:00
Removes some of the code duplication for UarteWithIdle
This commit removes some of the code duplication for UarteWithIdle at the expense of requiring a split. As the example illustrates though, this expense seems worth the benefit in terms of maintenance, and the avoidance of copying over methods. My main motivation for this commit was actually due to the `event_endtx` method not having been copied across.
This commit is contained in:
huntc
parent
f8fd6ab208
commit
e1faf88607
@ -173,6 +173,61 @@ impl<'d, T: Instance> Uarte<'d, T> {
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(self.tx, self.rx)
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}
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/// Split the Uarte into a transmitter and receiver that will
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/// return on idle, which is determined as the time it takes
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/// for two bytes to be received.
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pub fn split_with_idle<U: TimerInstance>(
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self,
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timer: impl Peripheral<P = U> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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) -> (UarteTx<'d, T>, UarteRxWithIdle<'d, T, U>) {
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let mut timer = Timer::new(timer);
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into_ref!(ppi_ch1, ppi_ch2);
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let r = T::regs();
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// BAUDRATE register values are `baudrate * 2^32 / 16000000`
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// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
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//
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// We want to stop RX if line is idle for 2 bytes worth of time
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// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
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// This gives us the amount of 16M ticks for 20 bits.
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let baudrate = r.baudrate.read().baudrate().variant().unwrap();
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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timer.set_frequency(Frequency::F16MHz);
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timer.cc(0).write(timeout);
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timer.cc(0).short_compare_clear();
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timer.cc(0).short_compare_stop();
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let mut ppi_ch1 = Ppi::new_one_to_two(
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ppi_ch1.map_into(),
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Event::from_reg(&r.events_rxdrdy),
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timer.task_clear(),
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timer.task_start(),
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);
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ppi_ch1.enable();
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let mut ppi_ch2 = Ppi::new_one_to_one(
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ppi_ch2.map_into(),
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timer.cc(0).event_compare(),
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Task::from_reg(&r.tasks_stoprx),
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);
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ppi_ch2.enable();
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(
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self.tx,
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UarteRxWithIdle {
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rx: self.rx,
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timer,
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ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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},
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)
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}
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/// Return the endtx event for use with PPI
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pub fn event_endtx(&self) -> Event {
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let r = T::regs();
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@ -597,6 +652,117 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> {
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}
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}
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pub struct UarteRxWithIdle<'d, T: Instance, U: TimerInstance> {
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rx: UarteRx<'d, T>,
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timer: Timer<'d, U>,
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ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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}
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impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.read(buffer).await
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.blocking_read(buffer)
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = T::regs();
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let s = T::state();
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self.ppi_ch1.enable();
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let drop = OnDrop::new(|| {
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self.timer.stop();
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r.intenclr.write(|w| w.endrx().clear());
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r.events_rxto.reset();
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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});
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenset.write(|w| w.endrx().set());
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compiler_fence(Ordering::SeqCst);
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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s.endrx_waker.register(cx.waker());
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if r.events_endrx.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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let n = r.rxd.amount.read().amount().bits() as usize;
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self.timer.stop();
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r.events_rxstarted.reset();
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drop.defuse();
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Ok(n)
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}
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pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = T::regs();
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self.ppi_ch1.enable();
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenclr.write(|w| w.endrx().clear());
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compiler_fence(Ordering::SeqCst);
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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compiler_fence(Ordering::SeqCst);
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let n = r.rxd.amount.read().amount().bits() as usize;
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self.timer.stop();
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r.events_rxstarted.reset();
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Ok(n)
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}
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}
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#[cfg(not(any(feature = "_nrf9160", feature = "nrf5340")))]
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pub(crate) fn apply_workaround_for_enable_anomaly(_r: &crate::pac::uarte0::RegisterBlock) {
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// Do nothing
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@ -665,270 +831,6 @@ pub(crate) fn drop_tx_rx(r: &pac::uarte0::RegisterBlock, s: &sealed::State) {
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}
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}
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/// Interface to an UARTE peripheral that uses an additional timer and two PPI channels,
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/// allowing it to implement the ReadUntilIdle trait.
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pub struct UarteWithIdle<'d, U: Instance, T: TimerInstance> {
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tx: UarteTx<'d, U>,
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rx: UarteRxWithIdle<'d, U, T>,
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}
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impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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/// Create a new UARTE without hardware flow control
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rxd, txd);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1,
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ppi_ch2,
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irq,
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rxd.map_into(),
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txd.map_into(),
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None,
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None,
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config,
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)
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}
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/// Create a new UARTE with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rxd, txd, cts, rts);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1,
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ppi_ch2,
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irq,
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rxd.map_into(),
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txd.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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config,
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)
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}
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fn new_inner(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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irq: impl Peripheral<P = U::Interrupt> + 'd,
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rxd: PeripheralRef<'d, AnyPin>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Self {
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let baudrate = config.baudrate;
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let (tx, rx) = Uarte::new_inner(uarte, irq, rxd, txd, cts, rts, config).split();
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let mut timer = Timer::new(timer);
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into_ref!(ppi_ch1, ppi_ch2);
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let r = U::regs();
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// BAUDRATE register values are `baudrate * 2^32 / 16000000`
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// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
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//
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// We want to stop RX if line is idle for 2 bytes worth of time
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// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
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// This gives us the amount of 16M ticks for 20 bits.
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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timer.set_frequency(Frequency::F16MHz);
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timer.cc(0).write(timeout);
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timer.cc(0).short_compare_clear();
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timer.cc(0).short_compare_stop();
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let mut ppi_ch1 = Ppi::new_one_to_two(
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ppi_ch1.map_into(),
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Event::from_reg(&r.events_rxdrdy),
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timer.task_clear(),
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timer.task_start(),
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);
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ppi_ch1.enable();
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let mut ppi_ch2 = Ppi::new_one_to_one(
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ppi_ch2.map_into(),
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timer.cc(0).event_compare(),
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Task::from_reg(&r.tasks_stoprx),
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);
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ppi_ch2.enable();
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Self {
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tx,
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rx: UarteRxWithIdle {
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rx,
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timer,
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ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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},
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}
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}
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/// Split the Uarte into a transmitter and receiver, which is
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/// particuarly useful when having two tasks correlating to
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/// transmitting and receiving.
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pub fn split(self) -> (UarteTx<'d, U>, UarteRxWithIdle<'d, U, T>) {
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(self.tx, self.rx)
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.read(buffer).await
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write(buffer).await
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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self.rx.read_until_idle(buffer).await
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}
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pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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self.rx.blocking_read_until_idle(buffer)
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}
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}
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pub struct UarteRxWithIdle<'d, U: Instance, T: TimerInstance> {
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rx: UarteRx<'d, U>,
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timer: Timer<'d, T>,
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ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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}
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impl<'d, U: Instance, T: TimerInstance> UarteRxWithIdle<'d, U, T> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.read(buffer).await
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.blocking_read(buffer)
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = U::regs();
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let s = U::state();
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self.ppi_ch1.enable();
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let drop = OnDrop::new(|| {
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self.timer.stop();
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r.intenclr.write(|w| w.endrx().clear());
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r.events_rxto.reset();
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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});
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenset.write(|w| w.endrx().set());
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compiler_fence(Ordering::SeqCst);
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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s.endrx_waker.register(cx.waker());
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if r.events_endrx.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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let n = r.rxd.amount.read().amount().bits() as usize;
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self.timer.stop();
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r.events_rxstarted.reset();
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drop.defuse();
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Ok(n)
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}
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pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = U::regs();
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self.ppi_ch1.enable();
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenclr.write(|w| w.endrx().clear());
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compiler_fence(Ordering::SeqCst);
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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compiler_fence(Ordering::SeqCst);
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let n = r.rxd.amount.read().amount().bits() as usize;
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self.timer.stop();
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r.events_rxstarted.reset();
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Ok(n)
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}
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}
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pub(crate) mod sealed {
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use core::sync::atomic::AtomicU8;
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@ -1006,18 +908,6 @@ mod eh02 {
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Ok(())
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}
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}
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impl<'d, U: Instance, T: TimerInstance> embedded_hal_02::blocking::serial::Write<u8> for UarteWithIdle<'d, U, T> {
|
||||
type Error = Error;
|
||||
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
self.blocking_write(buffer)
|
||||
}
|
||||
|
||||
fn bflush(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(feature = "unstable-traits")]
|
||||
@ -1067,10 +957,6 @@ mod eh1 {
|
||||
impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for UarteRx<'d, T> {
|
||||
type Error = Error;
|
||||
}
|
||||
|
||||
impl<'d, U: Instance, T: TimerInstance> embedded_hal_1::serial::ErrorType for UarteWithIdle<'d, U, T> {
|
||||
type Error = Error;
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(all(
|
||||
@ -1126,26 +1012,4 @@ mod eha {
|
||||
self.read(buffer)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, U: Instance, T: TimerInstance> embedded_hal_async::serial::Read for UarteWithIdle<'d, U, T> {
|
||||
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
||||
|
||||
fn read<'a>(&'a mut self, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
||||
self.read(buffer)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, U: Instance, T: TimerInstance> embedded_hal_async::serial::Write for UarteWithIdle<'d, U, T> {
|
||||
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
||||
|
||||
fn write<'a>(&'a mut self, buffer: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
self.write(buffer)
|
||||
}
|
||||
|
||||
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
||||
|
||||
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
||||
async move { Ok(()) }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -15,7 +15,8 @@ async fn main(_spawner: Spawner) {
|
||||
config.baudrate = uarte::Baudrate::BAUD115200;
|
||||
|
||||
let irq = interrupt::take!(UARTE0_UART0);
|
||||
let mut uart = uarte::UarteWithIdle::new(p.UARTE0, p.TIMER0, p.PPI_CH0, p.PPI_CH1, irq, p.P0_08, p.P0_06, config);
|
||||
let uart = uarte::Uarte::new(p.UARTE0, irq, p.P0_08, p.P0_06, config);
|
||||
let (mut tx, mut rx) = uart.split_with_idle(p.TIMER0, p.PPI_CH0, p.PPI_CH1);
|
||||
|
||||
info!("uarte initialized!");
|
||||
|
||||
@ -23,12 +24,12 @@ async fn main(_spawner: Spawner) {
|
||||
let mut buf = [0; 8];
|
||||
buf.copy_from_slice(b"Hello!\r\n");
|
||||
|
||||
unwrap!(uart.write(&buf).await);
|
||||
unwrap!(tx.write(&buf).await);
|
||||
info!("wrote hello in uart!");
|
||||
|
||||
loop {
|
||||
info!("reading...");
|
||||
let n = unwrap!(uart.read_until_idle(&mut buf).await);
|
||||
let n = unwrap!(rx.read_until_idle(&mut buf).await);
|
||||
info!("got {} bytes", n);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user