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nrf: rename inner peripheral to peri for consistence

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This commit is contained in:
Dario Nieuwenhuis 2021-03-21 21:57:04 +01:00
parent 90a2b823a4
commit d5ff1a0ae3
2 changed files with 13 additions and 13 deletions
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18
embassy-nrf/src/qspi.rs
View File

@ -44,7 +44,7 @@ pub struct Config {
} }
pub struct Qspi<'d, T: Instance> { pub struct Qspi<'d, T: Instance> {
qspi: T, peri: T,
irq: T::Interrupt, irq: T::Interrupt,
phantom: PhantomData<&'d mut T>, phantom: PhantomData<&'d mut T>,
} }
@ -131,14 +131,14 @@ impl<'d, T: Instance> Qspi<'d, T> {
r.events_ready.reset(); r.events_ready.reset();
Self { Self {
qspi, peri: qspi,
irq, irq,
phantom: PhantomData, phantom: PhantomData,
} }
} }
pub fn sleep(mut self: Pin<&mut Self>) { pub fn sleep(mut self: Pin<&mut Self>) {
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
info!("flash: sleeping"); info!("flash: sleeping");
info!("flash: state = {:?}", r.status.read().bits()); info!("flash: state = {:?}", r.status.read().bits());
@ -177,7 +177,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
let len = core::cmp::max(req.len(), resp.len()) as u8; let len = core::cmp::max(req.len(), resp.len()) as u8;
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
r.cinstrdat0.write(|w| unsafe { w.bits(dat0) }); r.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
r.cinstrdat1.write(|w| unsafe { w.bits(dat1) }); r.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
@ -198,7 +198,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
self.as_mut().wait_ready().await; self.as_mut().wait_ready().await;
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
let dat0 = r.cinstrdat0.read().bits(); let dat0 = r.cinstrdat0.read().bits();
let dat1 = r.cinstrdat1.read().bits(); let dat1 = r.cinstrdat1.read().bits();
@ -222,7 +222,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
let this = unsafe { self.get_unchecked_mut() }; let this = unsafe { self.get_unchecked_mut() };
poll_fn(move |cx| { poll_fn(move |cx| {
let r = this.qspi.regs(); let r = this.peri.regs();
if r.events_ready.read().bits() != 0 { if r.events_ready.read().bits() != 0 {
r.events_ready.reset(); r.events_ready.reset();
@ -257,7 +257,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
assert_eq!(data.len() as u32 % 4, 0); assert_eq!(data.len() as u32 % 4, 0);
assert_eq!(address as u32 % 4, 0); assert_eq!(address as u32 % 4, 0);
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
r.read r.read
.src .src
@ -293,7 +293,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
assert_eq!(data.len() as u32 % 4, 0); assert_eq!(data.len() as u32 % 4, 0);
assert_eq!(address as u32 % 4, 0); assert_eq!(address as u32 % 4, 0);
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
r.write r.write
.src .src
.write(|w| unsafe { w.src().bits(data.as_ptr() as u32) }); .write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
@ -322,7 +322,7 @@ impl<'d, T: Instance> Flash for Qspi<'d, T> {
assert_eq!(address as u32 % 4096, 0); assert_eq!(address as u32 % 4096, 0);
let r = unsafe { self.as_mut().get_unchecked_mut() }.qspi.regs(); let r = unsafe { self.as_mut().get_unchecked_mut() }.peri.regs();
r.erase r.erase
.ptr .ptr
.write(|w| unsafe { w.ptr().bits(address as u32) }); .write(|w| unsafe { w.ptr().bits(address as u32) });

8
embassy-nrf/src/spim.rs
View File

@ -26,7 +26,7 @@ pub enum Error {
} }
pub struct Spim<'d, T: Instance> { pub struct Spim<'d, T: Instance> {
spim: T, peri: T,
irq: T::Interrupt, irq: T::Interrupt,
phantom: PhantomData<&'d mut T>, phantom: PhantomData<&'d mut T>,
} }
@ -116,7 +116,7 @@ impl<'d, T: Instance> Spim<'d, T> {
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
Self { Self {
spim, peri: spim,
irq, irq,
phantom: PhantomData, phantom: PhantomData,
} }
@ -155,7 +155,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
// before any DMA action has started. // before any DMA action has started.
compiler_fence(Ordering::SeqCst); compiler_fence(Ordering::SeqCst);
let r = this.spim.regs(); let r = this.peri.regs();
// Set up the DMA write. // Set up the DMA write.
r.txd r.txd
@ -187,7 +187,7 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
// Wait for 'end' event. // Wait for 'end' event.
poll_fn(|cx| { poll_fn(|cx| {
let r = this.spim.regs(); let r = this.peri.regs();
if r.events_end.read().bits() != 0 { if r.events_end.read().bits() != 0 {
r.events_end.reset(); r.events_end.reset();