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Merge pull request #3319 from badrbouslikhin/buffered-uart-rx-fix

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fix(stm32): fix dma and idle line detection in ringbuffereduartrx
This commit is contained in:
Dario Nieuwenhuis 2024-09-10 21:30:22 +00:00 committed by GitHub
commit d5e77f69c1
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GPG Key ID: B5690EEEBB952194
2 changed files with 18 additions and 17 deletions
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1
embassy-stm32/src/dma/dma_bdma.rs
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@ -777,6 +777,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
let dir = Dir::PeripheralToMemory;
let data_size = W::size();
options.half_transfer_ir = true;
options.complete_transfer_ir = true;
options.circular = true;

34
embassy-stm32/src/usart/ringbuffered.rs
View File

@ -184,20 +184,6 @@ impl<'d> RingBufferedUartRx<'d> {
async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> {
compiler_fence(Ordering::SeqCst);
let mut dma_init = false;
// Future which completes when there is dma is half full or full
let dma = poll_fn(|cx| {
self.ring_buf.set_waker(cx.waker());
let status = match dma_init {
false => Poll::Pending,
true => Poll::Ready(()),
};
dma_init = true;
status
});
// Future which completes when idle line is detected
let s = self.state;
let uart = poll_fn(|cx| {
@ -219,9 +205,23 @@ impl<'d> RingBufferedUartRx<'d> {
}
});
match select(dma, uart).await {
Either::Left(((), _)) => Ok(()),
Either::Right((result, _)) => result,
let mut dma_init = false;
// Future which completes when there is dma is half full or full
let dma = poll_fn(|cx| {
self.ring_buf.set_waker(cx.waker());
let status = match dma_init {
false => Poll::Pending,
true => Poll::Ready(()),
};
dma_init = true;
status
});
match select(uart, dma).await {
Either::Left((result, _)) => result,
Either::Right(((), _)) => Ok(()),
}
}
}