stm32: remove last few mod sealed's.

This commit is contained in:
Dario Nieuwenhuis 2024-04-05 00:48:19 +02:00
parent a84b33995e
commit d597815c9a
3 changed files with 131 additions and 139 deletions

View File

@ -3,6 +3,7 @@
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
use crate::pac::cordic::vals;
use crate::{dma, peripherals};
mod enums;
@ -11,9 +12,6 @@ pub use enums::*;
mod errors;
pub use errors::*;
mod sealed;
use self::sealed::SealedInstance;
pub mod utils;
/// CORDIC driver
@ -22,6 +20,120 @@ pub struct Cordic<'d, T: Instance> {
config: Config,
}
/// Cordic instance
trait SealedInstance {
/// Get access to CORDIC registers
fn regs() -> crate::pac::cordic::Cordic;
/// Set Function value
fn set_func(&self, func: Function) {
Self::regs()
.csr()
.modify(|v| v.set_func(vals::Func::from_bits(func as u8)));
}
/// Set Precision value
fn set_precision(&self, precision: Precision) {
Self::regs()
.csr()
.modify(|v| v.set_precision(vals::Precision::from_bits(precision as u8)))
}
/// Set Scale value
fn set_scale(&self, scale: Scale) {
Self::regs()
.csr()
.modify(|v| v.set_scale(vals::Scale::from_bits(scale as u8)))
}
/// Enable global interrupt
fn enable_irq(&self) {
Self::regs().csr().modify(|v| v.set_ien(true))
}
/// Disable global interrupt
fn disable_irq(&self) {
Self::regs().csr().modify(|v| v.set_ien(false))
}
/// Enable Read DMA
fn enable_read_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmaren(true);
})
}
/// Disable Read DMA
fn disable_read_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmaren(false);
})
}
/// Enable Write DMA
fn enable_write_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmawen(true);
})
}
/// Disable Write DMA
fn disable_write_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmawen(false);
})
}
/// Set NARGS value
fn set_argument_count(&self, n: AccessCount) {
Self::regs().csr().modify(|v| {
v.set_nargs(match n {
AccessCount::One => vals::Num::NUM1,
AccessCount::Two => vals::Num::NUM2,
})
})
}
/// Set NRES value
fn set_result_count(&self, n: AccessCount) {
Self::regs().csr().modify(|v| {
v.set_nres(match n {
AccessCount::One => vals::Num::NUM1,
AccessCount::Two => vals::Num::NUM2,
});
})
}
/// Set ARGSIZE and RESSIZE value
fn set_data_width(&self, arg: Width, res: Width) {
Self::regs().csr().modify(|v| {
v.set_argsize(match arg {
Width::Bits32 => vals::Size::BITS32,
Width::Bits16 => vals::Size::BITS16,
});
v.set_ressize(match res {
Width::Bits32 => vals::Size::BITS32,
Width::Bits16 => vals::Size::BITS16,
})
})
}
/// Read RRDY flag
fn ready_to_read(&self) -> bool {
Self::regs().csr().read().rrdy()
}
/// Write value to WDATA
fn write_argument(&self, arg: u32) {
Self::regs().wdata().write_value(arg)
}
/// Read value from RDATA
fn read_result(&self) -> u32 {
Self::regs().rdata().read()
}
}
/// CORDIC instance trait
#[allow(private_bounds)]
pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral {}

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@ -1,116 +0,0 @@
use super::*;
use crate::pac::cordic::vals;
/// Cordic instance
pub(super) trait SealedInstance {
/// Get access to CORDIC registers
fn regs() -> crate::pac::cordic::Cordic;
/// Set Function value
fn set_func(&self, func: Function) {
Self::regs()
.csr()
.modify(|v| v.set_func(vals::Func::from_bits(func as u8)));
}
/// Set Precision value
fn set_precision(&self, precision: Precision) {
Self::regs()
.csr()
.modify(|v| v.set_precision(vals::Precision::from_bits(precision as u8)))
}
/// Set Scale value
fn set_scale(&self, scale: Scale) {
Self::regs()
.csr()
.modify(|v| v.set_scale(vals::Scale::from_bits(scale as u8)))
}
/// Enable global interrupt
fn enable_irq(&self) {
Self::regs().csr().modify(|v| v.set_ien(true))
}
/// Disable global interrupt
fn disable_irq(&self) {
Self::regs().csr().modify(|v| v.set_ien(false))
}
/// Enable Read DMA
fn enable_read_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmaren(true);
})
}
/// Disable Read DMA
fn disable_read_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmaren(false);
})
}
/// Enable Write DMA
fn enable_write_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmawen(true);
})
}
/// Disable Write DMA
fn disable_write_dma(&self) {
Self::regs().csr().modify(|v| {
v.set_dmawen(false);
})
}
/// Set NARGS value
fn set_argument_count(&self, n: AccessCount) {
Self::regs().csr().modify(|v| {
v.set_nargs(match n {
AccessCount::One => vals::Num::NUM1,
AccessCount::Two => vals::Num::NUM2,
})
})
}
/// Set NRES value
fn set_result_count(&self, n: AccessCount) {
Self::regs().csr().modify(|v| {
v.set_nres(match n {
AccessCount::One => vals::Num::NUM1,
AccessCount::Two => vals::Num::NUM2,
});
})
}
/// Set ARGSIZE and RESSIZE value
fn set_data_width(&self, arg: Width, res: Width) {
Self::regs().csr().modify(|v| {
v.set_argsize(match arg {
Width::Bits32 => vals::Size::BITS32,
Width::Bits16 => vals::Size::BITS16,
});
v.set_ressize(match res {
Width::Bits32 => vals::Size::BITS32,
Width::Bits16 => vals::Size::BITS16,
})
})
}
/// Read RRDY flag
fn ready_to_read(&self) -> bool {
Self::regs().csr().read().rrdy()
}
/// Write value to WDATA
fn write_argument(&self, arg: u32) {
Self::regs().wdata().write_value(arg)
}
/// Read value from RDATA
fn read_result(&self) -> u32 {
Self::regs().rdata().read()
}
}

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@ -105,27 +105,23 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
}
}
pub(crate) use sealed::State;
pub(crate) mod sealed {
use super::*;
pub struct State {
pub(crate) rx_waker: AtomicWaker,
pub(crate) rx_buf: RingBuffer,
pub(crate) tx_waker: AtomicWaker,
pub(crate) tx_buf: RingBuffer,
pub(crate) tx_done: AtomicBool,
}
pub(crate) struct State {
pub(crate) rx_waker: AtomicWaker,
pub(crate) rx_buf: RingBuffer,
pub(crate) tx_waker: AtomicWaker,
pub(crate) tx_buf: RingBuffer,
pub(crate) tx_done: AtomicBool,
}
impl State {
/// Create new state
pub const fn new() -> Self {
Self {
rx_buf: RingBuffer::new(),
tx_buf: RingBuffer::new(),
rx_waker: AtomicWaker::new(),
tx_waker: AtomicWaker::new(),
tx_done: AtomicBool::new(true),
}
impl State {
/// Create new state
pub(crate) const fn new() -> Self {
Self {
rx_buf: RingBuffer::new(),
tx_buf: RingBuffer::new(),
rx_waker: AtomicWaker::new(),
tx_waker: AtomicWaker::new(),
tx_done: AtomicBool::new(true),
}
}
}