mirror of
https://github.com/embassy-rs/embassy.git
synced 2024-11-21 22:32:29 +00:00
embassy-stm32: Misc clippy fixes
This commit is contained in:
Grant Miller
parent
477a90b8e3
commit
d49f40dd5c
@ -116,6 +116,7 @@ macro_rules! impl_peripheral {
|
||||
|
||||
#[inline]
|
||||
unsafe fn clone_unchecked(&self) -> Self::P {
|
||||
#[allow(clippy::needless_update)]
|
||||
$type { ..*self }
|
||||
}
|
||||
}
|
||||
|
||||
@ -126,7 +126,7 @@ fn main() {
|
||||
_ => panic!("unknown time_driver {:?}", time_driver),
|
||||
};
|
||||
|
||||
if time_driver_singleton != "" {
|
||||
if !time_driver_singleton.is_empty() {
|
||||
println!("cargo:rustc-cfg=time_driver_{}", time_driver_singleton.to_lowercase());
|
||||
}
|
||||
|
||||
@ -634,7 +634,7 @@ fn main() {
|
||||
|| regs.version.starts_with("h7")
|
||||
|| regs.version.starts_with("f4")
|
||||
{
|
||||
peri = format_ident!("{}", pin.signal.replace("_", ""));
|
||||
peri = format_ident!("{}", pin.signal.replace('_', ""));
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
@ -774,10 +774,11 @@ fn main() {
|
||||
.filter(|m| m.kind == MemoryRegionKind::Flash && m.settings.is_some())
|
||||
{
|
||||
let settings = m.settings.as_ref().unwrap();
|
||||
let mut row = Vec::new();
|
||||
row.push(get_flash_region_type_name(m.name));
|
||||
row.push(settings.write_size.to_string());
|
||||
row.push(settings.erase_size.to_string());
|
||||
let row = vec![
|
||||
get_flash_region_type_name(m.name),
|
||||
settings.write_size.to_string(),
|
||||
settings.erase_size.to_string(),
|
||||
];
|
||||
flash_regions_table.push(row);
|
||||
}
|
||||
|
||||
@ -787,7 +788,7 @@ fn main() {
|
||||
for p in METADATA.peripherals {
|
||||
if let Some(regs) = &p.registers {
|
||||
if regs.kind == "gpio" {
|
||||
let port_letter = p.name.chars().skip(4).next().unwrap();
|
||||
let port_letter = p.name.chars().nth(4).unwrap();
|
||||
assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
|
||||
let port_num = (p.address as u32 - gpio_base) / gpio_stride;
|
||||
|
||||
@ -804,18 +805,17 @@ fn main() {
|
||||
}
|
||||
|
||||
for irq in p.interrupts {
|
||||
let mut row = Vec::new();
|
||||
row.push(p.name.to_string());
|
||||
row.push(regs.kind.to_string());
|
||||
row.push(regs.block.to_string());
|
||||
row.push(irq.signal.to_string());
|
||||
row.push(irq.interrupt.to_ascii_uppercase());
|
||||
let row = vec![
|
||||
p.name.to_string(),
|
||||
regs.kind.to_string(),
|
||||
regs.block.to_string(),
|
||||
irq.signal.to_string(),
|
||||
irq.interrupt.to_ascii_uppercase(),
|
||||
];
|
||||
interrupts_table.push(row)
|
||||
}
|
||||
|
||||
let mut row = Vec::new();
|
||||
row.push(regs.kind.to_string());
|
||||
row.push(p.name.to_string());
|
||||
let row = vec![regs.kind.to_string(), p.name.to_string()];
|
||||
peripherals_table.push(row);
|
||||
}
|
||||
}
|
||||
@ -975,7 +975,7 @@ macro_rules! {} {{
|
||||
.unwrap();
|
||||
|
||||
for row in data {
|
||||
write!(out, " __{}_inner!(({}));\n", name, row.join(",")).unwrap();
|
||||
writeln!(out, " __{}_inner!(({}));", name, row.join(",")).unwrap();
|
||||
}
|
||||
|
||||
write!(
|
||||
@ -999,5 +999,5 @@ fn get_flash_region_type_name(name: &str) -> String {
|
||||
get_flash_region_name(name)
|
||||
.replace("BANK", "Bank")
|
||||
.replace("REGION", "Region")
|
||||
.replace("_", "")
|
||||
.replace('_', "")
|
||||
}
|
||||
|
||||
@ -271,7 +271,7 @@ impl<'d, T: Instance> Can<'d, T> {
|
||||
} else {
|
||||
let stid = (rir.stid() & 0x7FF) as u32;
|
||||
let exid = rir.exid() & 0x3FFFF;
|
||||
let id = (stid << 18) | (exid as u32);
|
||||
let id = (stid << 18) | (exid);
|
||||
Id::from(ExtendedId::new_unchecked(id))
|
||||
};
|
||||
let data_len = fifo.rdtr().read().dlc() as usize;
|
||||
@ -383,7 +383,7 @@ impl<'d, T: Instance> Can<'d, T> {
|
||||
let sjw = 1;
|
||||
|
||||
// Pack into BTR register values
|
||||
Some((sjw - 1) << 24 | (bs1 as u32 - 1) << 16 | (bs2 as u32 - 1) << 20 | (prescaler as u32 - 1))
|
||||
Some((sjw - 1) << 24 | (bs1 as u32 - 1) << 16 | (bs2 as u32 - 1) << 20 | (prescaler - 1))
|
||||
}
|
||||
|
||||
pub fn split<'c>(&'c self) -> (CanTx<'c, 'd, T>, CanRx<'c, 'd, T>) {
|
||||
|
||||
@ -356,7 +356,7 @@ mod tests {
|
||||
pub fn new(len: usize) -> Self {
|
||||
Self {
|
||||
requests: cell::RefCell::new(vec![]),
|
||||
len: len,
|
||||
len,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -147,7 +147,7 @@ pub(super) unsafe fn erase_sector_unlocked(sector: &FlashSector) -> Result<(), E
|
||||
|
||||
let _on_drop = OnDrop::new(|| family::lock());
|
||||
|
||||
family::blocking_erase_sector(§or)
|
||||
family::blocking_erase_sector(sector)
|
||||
}
|
||||
|
||||
pub(super) unsafe fn erase_sector_with_critical_section(sector: &FlashSector) -> Result<(), Error> {
|
||||
|
||||
@ -777,12 +777,14 @@ mod eh02 {
|
||||
|
||||
#[inline]
|
||||
fn set_high(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_high())
|
||||
self.set_high();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn set_low(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_low())
|
||||
self.set_low();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
@ -803,7 +805,8 @@ mod eh02 {
|
||||
type Error = Infallible;
|
||||
#[inline]
|
||||
fn toggle(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.toggle())
|
||||
self.toggle();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
@ -812,12 +815,14 @@ mod eh02 {
|
||||
|
||||
#[inline]
|
||||
fn set_high(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_high())
|
||||
self.set_high();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn set_low(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_low())
|
||||
self.set_low();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
@ -838,7 +843,8 @@ mod eh02 {
|
||||
type Error = Infallible;
|
||||
#[inline]
|
||||
fn toggle(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.toggle())
|
||||
self.toggle();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
@ -861,12 +867,14 @@ mod eh02 {
|
||||
|
||||
#[inline]
|
||||
fn set_high(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_high())
|
||||
self.set_high();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn set_low(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.set_low())
|
||||
self.set_low();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
@ -887,7 +895,8 @@ mod eh02 {
|
||||
type Error = Infallible;
|
||||
#[inline]
|
||||
fn toggle(&mut self) -> Result<(), Self::Error> {
|
||||
Ok(self.toggle())
|
||||
self.toggle();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -21,21 +21,12 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
|
||||
}
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Copy, Clone)]
|
||||
#[derive(Copy, Clone, Default)]
|
||||
pub struct Config {
|
||||
pub sda_pullup: bool,
|
||||
pub scl_pullup: bool,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
sda_pullup: false,
|
||||
scl_pullup: false,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct State {}
|
||||
|
||||
impl State {
|
||||
@ -90,7 +81,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
//reg.set_anfoff(false);
|
||||
});
|
||||
|
||||
let timings = Timings::new(T::frequency(), freq.into());
|
||||
let timings = Timings::new(T::frequency(), freq);
|
||||
|
||||
T::regs().cr2().modify(|reg| {
|
||||
reg.set_freq(timings.freq);
|
||||
@ -461,7 +452,7 @@ impl Timings {
|
||||
let speed = speed.0;
|
||||
let clock = i2cclk.0;
|
||||
let freq = clock / 1_000_000;
|
||||
assert!(freq >= 2 && freq <= 50);
|
||||
assert!((2..=50).contains(&freq));
|
||||
|
||||
// Configure bus frequency into I2C peripheral
|
||||
let trise = if speed <= 100_000 {
|
||||
|
||||
@ -223,7 +223,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let pclk = T::frequency();
|
||||
let freq = config.frequency;
|
||||
let br = compute_baud_rate(pclk, freq.into());
|
||||
let br = compute_baud_rate(pclk, freq);
|
||||
|
||||
let cpha = config.raw_phase();
|
||||
let cpol = config.raw_polarity();
|
||||
@ -331,7 +331,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
|
||||
let pclk = T::frequency();
|
||||
let freq = config.frequency;
|
||||
let br = compute_baud_rate(pclk, freq.into());
|
||||
let br = compute_baud_rate(pclk, freq);
|
||||
|
||||
#[cfg(any(spi_v1, spi_f1, spi_v2))]
|
||||
T::REGS.cr1().modify(|w| {
|
||||
@ -447,7 +447,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
where
|
||||
Tx: TxDma<T>,
|
||||
{
|
||||
if data.len() == 0 {
|
||||
if data.is_empty() {
|
||||
return Ok(());
|
||||
}
|
||||
|
||||
@ -481,7 +481,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
|
||||
Tx: TxDma<T>,
|
||||
Rx: RxDma<T>,
|
||||
{
|
||||
if data.len() == 0 {
|
||||
if data.is_empty() {
|
||||
return Ok(());
|
||||
}
|
||||
|
||||
@ -843,7 +843,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
|
||||
spin_until_rx_ready(regs)?;
|
||||
|
||||
let rx_word = unsafe { ptr::read_volatile(regs.rx_ptr()) };
|
||||
return Ok(rx_word);
|
||||
Ok(rx_word)
|
||||
}
|
||||
|
||||
mod eh02 {
|
||||
@ -978,7 +978,7 @@ mod word_impl {
|
||||
impl_word!(u16, vals::Dff::SIXTEENBIT);
|
||||
}
|
||||
|
||||
#[cfg(any(spi_v2))]
|
||||
#[cfg(spi_v2)]
|
||||
mod word_impl {
|
||||
use super::*;
|
||||
|
||||
|
||||
@ -186,9 +186,8 @@ fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
|
||||
error = this_error;
|
||||
}
|
||||
|
||||
match error {
|
||||
0 => break,
|
||||
_ => {}
|
||||
if error == 0 {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
|
||||
/// without the possibility of loosing bytes. The `dma_buf` is a buffer registered to the
|
||||
/// DMA controller, and must be sufficiently large, such that it will not overflow.
|
||||
pub fn into_ring_buffered(self, dma_buf: &'d mut [u8]) -> RingBufferedUartRx<'d, T, RxDma> {
|
||||
assert!(dma_buf.len() > 0 && dma_buf.len() <= 0xFFFF);
|
||||
assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
|
||||
|
||||
let request = self.rx_dma.request();
|
||||
let opts = Default::default();
|
||||
@ -111,10 +111,9 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> RingBufferedUartRx<'d, T, RxD
|
||||
let r = T::regs();
|
||||
|
||||
// Start background receive if it was not already started
|
||||
match r.cr3().read().dmar() {
|
||||
false => self.start()?,
|
||||
_ => {}
|
||||
};
|
||||
if !r.cr3().read().dmar() {
|
||||
self.start()?;
|
||||
}
|
||||
|
||||
check_for_errors(clear_idle_flag(T::regs()))?;
|
||||
|
||||
|
||||
@ -60,9 +60,7 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> {
|
||||
rl
|
||||
);
|
||||
|
||||
IndependentWatchdog {
|
||||
wdg: PhantomData::default(),
|
||||
}
|
||||
IndependentWatchdog { wdg: PhantomData }
|
||||
}
|
||||
|
||||
pub fn unleash(&mut self) {
|
||||
@ -104,16 +102,16 @@ mod tests {
|
||||
assert_eq!(512_000, get_timeout_us(4, MAX_RL));
|
||||
|
||||
assert_eq!(8_000, get_timeout_us(256, 0));
|
||||
assert_eq!(32768_000, get_timeout_us(256, MAX_RL));
|
||||
assert_eq!(32_768_000, get_timeout_us(256, MAX_RL));
|
||||
|
||||
assert_eq!(8000_000, get_timeout_us(64, 3999));
|
||||
assert_eq!(8_000_000, get_timeout_us(64, 3999));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn can_compute_reload_value() {
|
||||
assert_eq!(0xFFF, reload_value(4, 512_000));
|
||||
assert_eq!(0xFFF, reload_value(256, 32768_000));
|
||||
assert_eq!(0xFFF, reload_value(256, 32_768_000));
|
||||
|
||||
assert_eq!(3999, reload_value(64, 8000_000));
|
||||
assert_eq!(3999, reload_value(64, 8_000_000));
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user